Datasheet

Monitor Module (MON)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor 225
18.3.1.1 Normal Monitor Mode
When V
TST
is applied to IRQ and PTC3 is low upon monitor mode entry, the bus frequency is a
divide-by-two of the input clock. If PTC3 is high with V
TST
applied to IRQ upon monitor mode entry, the
bus frequency will be a divide-by-four of the input clock. Holding the PTC3 pin low when entering monitor
mode causes a bypass of a divide-by-two stage at the oscillator only if V
TST
is applied to IRQ. In this
Table 18-1. Monitor Mode Signal Requirements and Options
Mode IRQ RST
Reset
Vector
Serial
Communication
Mode
Selection
Divider
PLL COP
Communication
Speed
PTA0 PTA7 PTC0 PTC1 PTC3
External
Clock
Bus
Frequency
Baud
Rate
Normal
Monitor
V
TST
V
DD
or
V
TST
X 1 0 1 0 0 OFF Disabled
4.9152
MHz
2.457 MHz 9600
V
TST
V
DD
or
V
TST
X 1 0 1 0 1 OFF Disabled
9.8304
MHz
2.457 MHz 9600
Forced
Monitor
V
DD
V
DD
$FFFF
(blank)
1 0 X X X OFF Disabled
9.8304
MHz
2.457 MHz 9600
V
SS
V
DD
$FFFF
(blank)
1 0 X X X ON Disabled
32.768
kHz
2.457 MHz 9600
User
V
DD
or
V
SS
V
DD
or
V
TST
Not
$FFFF X X X X X X Enabled X X X
MON08
Function
[Pin No.]
V
TST
[6]
RST
[4]
—
COM
[8]
SSEL
[10]
MOD0
[12]
MOD1
[14]
DIV4
[16]
——
OSC1
[13]
——
1. PTA0 must have a pullup resistor to V
DD
in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus
frequency / 256.
3. External clock is a 4.9152 MHz or 9.8304 MHz canned oscillator on OSC1 or a 32.768 kHz crystal on OSC1 and OSC2.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC 1 2 GND
NC 3 4
RST
NC 5 6
IRQ
NC 7 8 PTA0
NC 9 10 PTA7
NC 11 12 PTC0
OSC1 13 14 PTC1
V
DD
15 16 PTC3