Datasheet

5.0-V Control Timing
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor 239
19.7 5.0-V Control Timing
Characteristic
(1)
1. V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
DD
unless otherwise noted.
Symbol Min Max Unit
Frequency of operation
Crystal option
External clock option
(2)
2. No more than 10% duty cycle deviation from 50%
f
OSC
32
dc
100
32.8
kHz
MHz
Internal operating frequency
f
OP
(f
BUS
)
— 8.2 MHz
Internal clock period (1/f
OP
)t
CYC
122 — ns
RST input pulse width low
t
IRL
100 — ns
IRQ interrupt pulse width low
(edge-triggered)
t
ILIH
100 — ns
IRQ interrupt pulse period
t
ILIL
(3)
3. The minimum period, t
ILIL
or t
TLTL
, should not be less than the number of cycles it takes to execute the interrupt service
routine plus t
CYC
.
—
t
CYC
Notes: