Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908GP32 Data Sheet, Rev. 10
54 Freescale Semiconductor
Figure 4-1. ADC Block Diagram
NOTE
Connect the V
DDAD
pin to the same voltage potential as the V
DD
pin, and
connect the V
SSAD
pin to the same voltage potential as the V
SS
pin.
The V
DDAD
pin should be routed carefully for maximum noise immunity.
4.3.3 Conversion Time
Conversion starts after a write to the ADSCR. One conversion will take between 16 and 17 ADC clock
cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency.
INTERNAL
DATA BUS
READ DDRBx
WRITE DDRBx
RESET
WRITE PTBx
READ PTBx
PTBx
DDRBx
PTBx
INTERRUPT
LOGIC
CHANNEL
SELECT
ADC
CLOCK
GENERATOR
CONVERSION
COMPLETE
ADC
(V
ADIN
)
ADC CLOCK
CGMXCLK
BUS CLOCK
ADCH4–ADCH0
ADC DATA REGISTER
AIEN COCO
DISABLE
DISABLE
ADC CHANNEL x
ADIV2–ADIV0 ADICLK
VOLTAGE IN
16 to 17 ADC cycles
ADC frequency
Conversion time =
Number of bus cycles = conversion time × bus frequency