Datasheet

CGM Registers
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor 71
5.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL)
(See 5.5.1 PLL Control Register.)
• PLL bandwidth control register (PBWC)
(See 5.5.2 PLL Bandwidth Control Register.)
• PLL multiplier select register high (PMSH)
(See 5.5.3 PLL Multiplier Select Register High.)
• PLL multiplier select register low (PMSL)
(See 5.5.4 PLL Multiplier Select Register Low.)
• PLL VCO range select register (PMRS)
(See 5.5.5 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS)
(See 5.5.6 PLL Reference Divider Select Register.)
Figure 5-3 is a summary of the CGM registers.
Addr. Register Name Bit 7 654321Bit 0
$0036
PLL Control Register
(PCTL)
Read:
PLLIE
PLLF
PLLON BCS PRE1 PRE0 VPR1 VPR0
Write:
Reset:00100000
$0037
PLL Bandwidth Control
Register
(PBWC)
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:00000000
$0038
PLL Multiplier Select High
Register
(PMSH)
Read: 0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
$0039
PLL Multiplier Select Low
Register
(PMSL)
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
$003A
PLL VCO Range Select
Register
(PMRS)
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
$003B
PLL Reference Divider
Select Register
(PMDS)
Read: 0000
RDS3 RDS2 RDS1 RDS0
Write:
Reset:00000001
= Unimplemented R = Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1,
ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 5-3. CGM I/O Register Summary