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M68HC08

Microcontrollers

freescale.com

MC68HC908GR16A

Data Sheet

MC68HC908GR16A

Rev. 1.0

03/2006

Summary of content (270 pages)

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MC68HC908GR16A Data Sheet M68HC08 Microcontrollers MC68HC908GR16A Rev. 1.0 03/2006 freescale.
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MC68HC908GR16A Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
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Revision History MC68HC908GR16A Data Sheet, Rev. 1.
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List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Chapters MC68HC908GR16A Data Sheet, Rev. 1.
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Table of Contents Chapter 1 General Description 1.1 1.2 1.2.1 1.2.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Features . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.
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4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 4.4.10 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.6 4.7 4.7.1 4.7.2 4.7.3 4.8 4.8.1 4.8.2 4.8.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 6.6 6.7 6.7.1 6.7.2 6.8 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 10 Low-Power Modes 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Analog-to-Digital Converter (ADC). . . . . . . . . . . . .
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Table of Contents Chapter 11 Low-Voltage Inhibit (LVI) 11.1 11.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.5 11.6 11.6.1 11.6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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.2.3.3 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3.4 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.4 System Integration Module (SIM) Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . 13.
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Table of Contents 14.5 14.5.1 14.5.2 14.6 14.7 14.7.1 14.7.2 14.8 14.8.1 14.8.2 14.8.3 14.8.4 14.8.5 14.8.6 14.8.7 14.8.8 14.9 14.9.1 14.9.2 14.9.3 14.9.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Chapter 17 Timebase Module (TBM) 17.1 17.2 17.3 17.4 17.5 17.6 17.6.1 17.6.2 17.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 19 Development Support 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2.1.1 Flag Protection During Break Interrupts . . . . . . . . .
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Table of Contents Chapter 21 Ordering Information and Mechanical Specifications 21.1 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 MC68HC908GR16A Data Sheet, Rev. 1.
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Chapter 1 General Description 1.1 Introduction The MC68HC908GR16A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.2 Features For convenience, features have been organized to reflect: • Standard features • Features of the CPU08 1.2.
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General Description • • • • • • • • • • • • • • • • • • • • Serial peripheral interface (SPI) module Enhanced serial communications interface (ESCI) module Fine adjust baud rate prescalers for precise control of baud rate Arbiter module: – Measurement of received bit timings for baud rate recovery without use of external timer – Bitwise arbitration for arbitrated UART communications LIN specific enhanced features: – Generation of LIN 1.
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MCU Block Diagram 1.2.2 Features of the CPU08 Features of the CPU08 include: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.
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General Description INTERNAL BUS DDRA PORTA PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1), (2) PTC3(1), (2) PTC2(1), (2) PTC1(1), (2) PTC0(1), (2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD DDRB SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE USER FLASH — 15,872 BYTES PTA7/KBD7– PTA0/KBD0(1) PORTB CONTROL AND STATUS REGISTERS — 64 BYTES
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CGMXFC VSSA VDDA PTC1 PTC0 PTA3/KBD3 30 29 28 27 26 25 1 OSC2 RST 31 32 OSC1 Pin Assignments 24 PTA2/KBD2 PTD1/MISO 6 19 PTB5/AD5 PTD2/MOSI 7 18 PTB4/AD4 PTD3/SPSCK 8 17 PTB3/AD3 16 VDDAD/VREFH PTB2/AD2 20 15 5 PTB1/AD1 PTD0/SS 14 VSSAD/VREFL PTB0/AD0 21 13 4 PTD6/T2CH0 IRQ 12 PTA0/KBD0 PTD5/T1CH1 22 11 3 PTD4/T1CH0 PTE1/RxD 10 PTA1/KBD1 VDD 23 9 2 VSS PTE0/TxD CGMXFC VSSA VDDA PTC1 PTC0 PTA7/KBD7 PTA6/KBD6 PTA5/KBD5 PTA4/KBD4 46 45
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General Description 1.5 Pin Functions Descriptions of the pin functions are provided here. 1.5.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4 shows. Place the C1 bypass capacitor as close to the MCU as possible.
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Pin Functions 1.5.5 CGM Power Supply Pins (VDDA and VSSA) VDDA and VSSA are the power supply pins for the analog portion of the clock generator module (CGM). Decoupling of these pins should be as per the digital supply. See Chapter 4 Clock Generator Module (CGM). 1.5.6 External Filter Capacitor Pin (VCGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Chapter 4 Clock Generator Module (CGM). 1.5.
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General Description 1.5.12 Port E I/O Pins (PTE5–PTE2 and PTE0/TxD) PTE5–PTE0 are general-purpose, bidirectional I/O port pins. PTE1 and PTE0 can also be programmed to be enhanced serial communications interface (ESCI) pins. PTE5–PTE2 are only available on the 48-pin LQFP package. See Chapter 14 Enhanced Serial Communications Interface (ESCI) Module and Chapter 12 Input/Output (I/O) Ports. NOTE Any unused inputs and I/O ports should be tied to an appropriate logic level (either VDD or VSS).
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Chapter 2 Memory 2.1 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 15,872 bytes of user FLASH memory • 1024 bytes of random-access memory (RAM) • 406 bytes of FLASH programming routines read-only memory (ROM) • 36 bytes of user-defined vectors • 350 bytes of monitor ROM 2.2 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset.
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Memory $0000 ↓ I/O REGISTERS 64 BYTES $003F $0040 ↓ RAM 1024 BYTES $043F $0440 ↓ UNIMPLEMENTED 192 BYTES $04FF $0500 ↓ RESERVED 128 BYTES INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 RESERVED $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 BREAK ADDRESS REGISTER HIGH (BRKH) $FE0A BREAK ADDRESS REGISTER LOW (BRKL) $FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR) $FE0C LVI STATUS REGISTER (LVISR) $FE10 ↓ $1C00 $
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Input/Output (I/O) Section Addr. $0000 Register Name Port A Data Register Read: (PTA) Write: See page 118. Reset: $0001 Port B Data Register Read: (PTB) Write: See page 120. Reset: $0002 Port C Data Register Read: (PTC) Write: See page 122. Reset: $0003 $0004 Port D Data Register Read: (PTD) Write: See page 124. Reset: Data Direction Register A Read: (DDRA) Write: See page 118. Reset: $0005 Data Direction Register B Read: (DDRB) Write: See page 121.
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Memory Addr. $000C $000D $000E $000F $0010 $0011 $0012 Register Name Data Direction Register E Read: (DDRE) Write: See page 128. Reset: Port C Input Pullup Enable Read: Register (PTCPUE) Write: See page 124. Reset: SPI Control Register Read: (SPCR) Write: See page 207. Reset: SPI Status and Control Read: Register (SPSCR) Write: See page 208. Reset: SPI Data Register Read: (SPDR) Write: See page 210. Reset: $0014 ESCI Control Register 2 Read: (SCC2) Write: See page 159.
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Input/Output (I/O) Section Addr. $0018 $0019 $001A $001B Register Name ESCI Data Register Read: (SCDR) Write: See page 164. Reset: ESCI Baud Rate Register Read: (SCBR) Write: See page 165. Reset: Keyboard Status Read: and Control Register Write: (INTKBSCR) See page 103. Reset: Keyboard Interrupt Enable Read: Register (INTKBIER) Write: See page 104.
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Memory Addr. $0024 $0025 $0026 $0027 Register Name Timer 1 Counter Modulo Read: Register Low (T1MODL) Write: See page 227. Reset: Timer 1 Channel 0 Status and Read: Control Register (T1SC0) Write: See page 230. Reset: Timer 1 Channel 0 Read: Register High (T1CH0H) Write: See page 230. Reset: Timer 1 Channel 0 Read: Register Low (T1CH0L) Write: See page 230. Reset: Timer 1 Channel 1 Status and Read: $0028 Control Register (T1SC1) Write: See page 230.
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Input/Output (I/O) Section Addr. Register Name Bit 7 Timer 2 Channel 0 Status and Read: $0030 Control Register (T2SC0) Write: See page 227. Reset: CH0F $0031 $0032 Timer 2 Channel 0 Read: Register High (T2CH0H) Write: See page 227. Reset: Timer 2 Channel 0 Read: Register Low (T2CH0L) Write: See page 230. Reset: Timer 2 Channel 1 Status and Read: $0033 Control Register (T2SC1) Write: See page 225. Reset: $0034 $0035 $0036 Timer 2 Channel 1 Read: Register High (T2CH1H) Write: See page 230.
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Memory Addr. $003C $003D $003E Register Name Bit 7 6 5 4 3 2 1 Bit 0 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 0 1 1 1 1 1 ADC Data High Register Read: (ADRH) Write: See page 53. Reset: 0 0 0 0 0 0 AD9 AD8 ADC Data Low Register Read: (ADRL) Write: See page 53. Reset: AD7 AD2 AD1 AD0 R ADC Status and Control Read: Register (ADSCR) Write: See page 51. Reset: COCO $003F ADC Clock Register Read: (ADCLK) Write: See page 55.
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Input/Output (I/O) Section Addr. $FE08 $FE09 Register Name FLASH Control Register Read: (FLCR) Write: See page 38. Reset: Break Address Register High Read: (BRKH) Write: See page 235. Reset: Break Address Register Low Read: $FE0A (BRKL) Write: See page 235. Reset: $FE0B Break Status and Control Read: Register (BRKSCR) Write: See page 235. Reset: Read: $FE0C $FF7E LVI Status Register (LVISR) Write: See page 113. Reset: FLASH Block Protect Read: Register (FLBPR)(1) Write: See page 43.
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Memory . Table 2-1.
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Random-Access Memory (RAM) 2.5 Random-Access Memory (RAM) Addresses $0040 through $043F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code.
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Memory 2.6.2 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 = Unimplemented Figure 2-3. FLASH Control Register (FLCR) HVEN — High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array.
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FLASH Memory (FLASH) 2.6.3 FLASH Page Erase Operation Use this step-by-step procedure to erase a page (64 bytes) of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 36-byte user interrupt vectors area also forms a page. Any FLASH memory page can be erased alone. 1. Set the ERASE bit, and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3.
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Memory NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. 2.6.5 FLASH Program/Read Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, and $XXE0.
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FLASH Memory (FLASH) NOTE Do not exceed tPROG maximum or tHV maximum. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) ≤ tHV maximum Refer to 20.15 Memory Characteristics.
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Memory Algorithm for programming a row (32 bytes) of FLASH memory 1 2 3 SET PGM BIT READ THE FLASH BLOCK PROTECT REGISTER WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 5 6 7 8 WAIT FOR A TIME, tNVS SET HVEN BIT WAIT FOR A TIME, tPGS WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME, tPROG COMPLETED PROGRAMMING THIS ROW? Y N 10 11 CLEAR PGM BIT WAIT FOR A TIME, tNVH Note: The time between each FLASH address change (step 7 to step 7), or the
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FLASH Memory (FLASH) 2.6.7 FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory. Address: $FF7E Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Reset: Unaffected by reset.
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Memory 2.6.8 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode. 2.6.
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Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the 10-bit analog-to-digital converter (ADC). 3.2 Features Features of the ADC module include: • Eight channels with multiplexed input • Linear successive approximation with monotonicity • 10-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock • Left or right justified result • Left justified sign data mode 3.
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Analog-to-Digital Converter (ADC) INTERNAL BUS DDRA PORTA PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1), (2) PTC3(1), (2) PTC2(1), (2) PTC1(1), (2) PTC0(1), (2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD DDRB SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE USER FLASH — 15,872 BYTES PTA7/KBD7– PTA0/KBD0(1) PORTB CONTROL AND STATUS REGISTE
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Functional Description INTERNAL DATA BUS READ DDRBx WRITE DDRBx DISABLE DDRBx RESET WRITE PTBx PTBx PTBx ADC CHANNEL x READ PTBx DISABLE ADC DATA REGISTER INTERRUPT LOGIC AIEN CONVERSION COMPLETE ADC ADC VOLTAGE IN (VADIN) CHANNEL SELECT ADCH4–ADCH0 ADC CLOCK COCO CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV2–ADIV0 ADICLK Figure 3-2. ADC Block Diagram 3.3.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $3FF (full scale).
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Analog-to-Digital Converter (ADC) 3.3.3 Conversion Time Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency. 16 to 17 ADC cycles Conversion time = ADC frequency Number of bus cycles = conversion time × bus frequency 3.3.4 Conversion In continuous conversion mode, the ADC data register will be filled with new data after each conversion.
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Monotonicity is used when compatibility with 8-bit ADC designs are required. No interlocking between ADRH and ADRL is present. NOTE Quantization error is affected when only the most significant eight bits are used as a result. See Figure 3-3.
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Analog-to-Digital Converter (ADC) 3.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the WAIT instruction. 3.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
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I/O Registers 3.7.4 ADC Voltage Reference Low Pin (VREFL) The ADC analog portion uses VREFL as its lower voltage reference pin. By default, connect the VREFH pin to the same voltage potential as VSS. External filtering is often necessary to ensure a clean VREFL for good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values.
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Analog-to-Digital Converter (ADC) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion.
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I/O Registers 3.8.2 ADC Data Register High and Data Register Low 3.8.2.1 Left Justified Mode In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read.
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Analog-to-Digital Converter (ADC) 3.8.2.3 Left Justified Signed Data Mode In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read.
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I/O Registers 3.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. Address: Read: Write: Reset: $003F Bit 7 6 5 4 3 2 1 ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 R 0 0 0 0 0 1 0 R = Reserved Bit 0 0 0 = Unimplemented Figure 3-9. ADC Clock Register (ADCLK) ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock.
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Analog-to-Digital Converter (ADC) MC68HC908GR16A Data Sheet, Rev. 1.
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Chapter 4 Clock Generator Module (CGM) 4.1 Introduction This section describes the clock generator module (CGM). The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
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Clock Generator Module (CGM) OSCILLATOR (OSC) OSC2 CGMXCLK (TO: SIM, TIMEBASE, ADC) OSC1 SIMOSCEN (FROM SIM) OSCENINSTOP (FROM CONFIG) PHASE-LOCKED LOOP (PLL) CGMRCLK CLOCK SELECT CIRCUIT BCS ÷2 A CGMOUT B S* (TO SIM) *WHEN S = 1, VDDA CGMXFC CGMOUT = B VSSA VPR1–VPR0 PTB4 VRS7–VRS0 PHASE DETECTOR MONITOR MODE VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER USER MODE CGMVCLK PLL ANALOG LOCK DETECTOR LOCK AUTOMATIC MODE CONTROL AUTO ACQ INTERRUPT CONTROL PLLIE CGMINT (TO SIM) PLLF MUL1
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Functional Description 4.3.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCENINSTOP bit in the CONFIG register enable the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency.
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Clock Generator Module (CGM) 4.3.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. (See 4.5.
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Functional Description The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 4.8 Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL control register (PCTL).
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Clock Generator Module (CGM) 4. Select a VCO frequency multiplier, N. ⎛ f VCLKDES⎞ N = round ⎜ --------------------------⎟ ⎝ f RCLK ⎠ 5. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS. f VCLK = ( N ) × f RCLK f BUS = ( f VCLK ) ⁄ 4 6. Select the VCO’s power-of-two range multiplier E, according to Table 4-2. Table 4-2. Power-of-Two Range Selectors Frequency Range E 0 < fVCLK ≤ 8 MHz 0 8 MHz< fVCLK ≤ 16 MHz 1 16 MHz< fVCLK ≤ 32 MHz 2(1) 1.
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Functional Description Table 4-3 provides numeric examples (register values are in hexadecimal notation): Table 4-3. Numeric Example fBUS (MHz) fRCLK (MHz) PCTL E PMSH,L N PMRS L 1.0 2.0 0 002 38 2.0 2.0 0 004 70 4.0 2.0 1 008 70 8.0 2.0 2 010 70 2.0 4.0 0 002 70 4.0 4.0 1 004 70 5.0 4.0 2 005 46 8.0 2.4576 4.0 4.9152 2 1 008 002 70 45 4.9152 4.9152 2 004 45 7.3728 4.9152 2 006 67 2.0 8.0 0 001 70 4.0 8.0 1 002 70 6.0 8.0 2 003 54 8.
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Clock Generator Module (CGM) 4.3.9 CGM External Connections In its typical configuration, the CGM requires external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 4-2. Figure 4-2 shows only the logical representation of the internal components and may not represent actual circuitry.
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I/O Signals 4.4 I/O Signals The following paragraphs describe the CGM I/O signals. 4.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 4.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 4.4.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure 4-2.
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Clock Generator Module (CGM) depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at start up. 4.4.9 CGM Base Clock Output (CGMOUT) CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two. 4.4.
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CGM Registers 4.5.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: Write: Reset: PLLIE 0 6 PLLF 5 4 3 2 1 Bit 0 PLLON BCS R R VPR1 VPR0 1 0 0 0 0 0 R = Reserved 0 = Unimplemented Figure 4-4.
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Clock Generator Module (CGM) BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See 4.3.8 Base Clock Selector Circuit.). VPR1 and VPR0 — VCO Power-of-Two Range Select Bits These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction with L controls the hardware center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when the PLLON bit is set. Reset clears these bits. (See 4.
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CGM Registers LOCK — Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as 0 and has no meaning. The write one function of this bit is reserved for test, so this bit must always be written as a 0. Reset clears the LOCK bit.
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Clock Generator Module (CGM) 4.5.4 PLL Multiplier Select Register Low The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider. Address: Read: Write: Reset: $0038 Bit 7 6 5 4 3 2 1 Bit 0 MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 0 1 0 0 0 0 0 0 Figure 4-7.
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Interrupts VRS7–VRS0 — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and 4.5.1 PLL Control Register.), controls the hardware center-of-range frequency, fVRS. VRS7–VRS0 cannot be written when the PLLON bit in the PCTL is set. (See 4.3.7 Special Programming Exceptions.
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Clock Generator Module (CGM) 4.7.2 Stop Mode If the OSCENINSTOP bit in the CONFIG2 register is cleared (default), then the STOP instruction disables the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the OSCENINSTOP bit in the CONFIG2 register is set, then the phase locked loop is shut off but the oscillator will continue to operate in stop mode. 4.7.
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Acquisition/Lock Time Specifications The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRCLK. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections.
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Clock Generator Module (CGM) Table 4-5. Example Filter Component Values fRCLK CF1 CF2 RF1 CF 1 MHz 8.2 nF 820 pF 2k 18 nF 2 MHz 4.7 nF 470 pF 2k 6.8 nF 3 MHz 3.3 nF 330 pF 2k 5.6 nF 4 MHz 2.2 nF 220 pF 2k 4.7 nF 5 MHz 1.8 nF 180 pF 2k 3.9 nF 6 MHz 1.5 nF 150 pF 2k 3.3 nF 7 MHz 1.2 nF 120 pF 2k 2.7 nF 8 MHz 1 nF 100 pF 2k 2.2 nF MC68HC908GR16A Data Sheet, Rev. 1.
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Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2.
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Configuration Register (CONFIG) Address: Read: Write: Reset: $001F Bit 7 6 5 4 3 2 1 Bit 0 COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD 0 0 0 0 See note 0 0 0 Note: LVI5OR3 bit is only reset via POR (power-on reset). Figure 5-2. Configuration Register 1 (CONFIG1) TBMCLKSEL— Timebase Clock Select Bit TBMCLKSEL enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables the extra prescaler and clearing this bit disables it.
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Functional Description LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. See Chapter 11 Low-Voltage Inhibit (LVI). 1 = LVI module power disabled 0 = LVI module power enabled LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module (see Chapter 11 Low-Voltage Inhibit (LVI)). The voltage mode selected for the LVI should match the operating VDD (see Chapter 20 Electrical Specifications) for the LVI’s voltage trip points for each of the modes.
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Configuration Register (CONFIG) MC68HC908GR16A Data Sheet, Rev. 1.
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Chapter 6 Computer Operating Properly (COP) Module 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register. 6.2 Functional Description Figure 6-1 shows the structure of the COP module.
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Computer Operating Properly (COP) Module The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 262,128 CGMXCLK cycle overflow option, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms.
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COP Control Register 6.3.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 6.3.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Chapter 5 Configuration Register (CONFIG). 6.3.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register.
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Computer Operating Properly (COP) Module 6.7.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction.
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Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.
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Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
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CPU Registers 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
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Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6.
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Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
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Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set.
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Instruction Set Summary Effect on CCR V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Description Operand Operation Opcode Source Form Address Mode Table
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Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP V H I N Z C Clear Compare A with M COM opr COMA COMX COM opr,X COM ,X COM opr,SP Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement DIV Divide INC opr INCA
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Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:
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Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
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Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
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MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
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Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 8.2 Features Features of the IRQ module include: • A dedicated external interrupt pin (IRQ) • IRQ interrupt control bits • Hysteresis buffer • Programmable edge-only or edge and level interrupt sensitivity • Automatic interrupt acknowledge • Internal pullup resistor 8.
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External Interrupt (IRQ) RESET INTERNAL ADDRESS BUS ACK TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF D CLR Q IRQ INTERRUPT REQUEST SYNCHRONIZER CK IRQ IMASK MODE TO MODE SELECT LOGIC HIGH VOLTAGE DETECT Figure 8-1.
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IRQ Pin 8.4 IRQ Pin A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level sensitive. With MODE set, both of the following actions must occur to clear IRQ: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
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External Interrupt (IRQ) 8.6 IRQ Status and Control Register The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin Address: Read: $001D Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 Write: Reset: ACK 0 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 = Unimplemented Figure 8-3.
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Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup device is also enabled on the pin. 9.
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Keyboard Interrupt Module (KBI) INTERNAL BUS DDRA PORTA PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1), (2) PTC3(1), (2) PTC2(1), (2) PTC1(1), (2) PTC0(1), (2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD DDRB SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE USER FLASH — 15,872 BYTES PTA7/KBD7– PTA0/KBD0(1) PORTB CONTROL AND STATUS REGISTERS
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Functional Description INTERNAL BUS VECTOR FETCH DECODER ACKK RESET KBD0 VDD . TO PULLUP ENABLE KEYF D CLR Q SYNCHRONIZER . CK KB0IE . KEYBOARD INTERRUPT REQUEST IMASKK KBD7 MODEK TO PULLUP ENABLE KB7IE Figure 9-2. Keyboard Module Block Diagram Addr. $001A $001B Register Name Keyboard Status Read: and Control Register Write: (INTKBSCR) See page 103. Reset: Keyboard Interrupt Enable Read: Register Write: (INTKBIER) See page 104.
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Keyboard Interrupt Module (KBI) The vector fetch or software clear and the return of all enabled keyboard interrupt pins to a high level may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays low.
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Keyboard Module During Break Interrupts 9.5.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 9.6 Keyboard Module During Break Interrupts The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state.
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Keyboard Interrupt Module (KBI) IMASKK — Keyboard Interrupt Mask Bit Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK.
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Chapter 10 Low-Power Modes 10.1 Introduction The microcontroller (MCU) may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution. This section describes how each module acts in the low-power modes. 10.1.1 Wait Mode The WAIT instruction puts the MCU in a low-power standby mode in which the central processor unit (CPU) clock is disabled but the bus clock continues to run.
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Low-Power Modes 10.3 Break Module (BRK) 10.3.1 Wait Mode The break (BRK) module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the break status register is set. 10.3.2 Stop Mode The break module is inactive in stop mode. The STOP instruction does not affect break module register states. 10.4 Central Processor Unit (CPU) 10.4.
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Computer Operating Properly Module (COP) 10.6 Computer Operating Properly Module (COP) 10.6.1 Wait Mode The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout. 10.6.2 Stop Mode Stop mode turns off the COPCLK input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the CONFIG1 register enables the STOP instruction.
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Low-Power Modes 10.9 Low-Voltage Inhibit Module (LVI) 10.9.1 Wait Mode If enabled, the low-voltage inhibit (LVI) module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 10.9.2 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. 10.10 Enhanced Serial Communications Interface Module (ESCI) 10.10.
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Timer Interface Module (TIM1 and TIM2) 10.12 Timer Interface Module (TIM1 and TIM2) 10.12.1 Wait Mode The timer interface modules (TIM) remain active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 10.12.2 Stop Mode The TIM is inactive in stop mode.
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Low-Power Modes • Timebase module (TBM) interrupt — A TBM interrupt loads the program counter with the contents of locations $FFDC and $FFDD when the timebase counter has rolled over. This allows the TBM to generate a periodic wakeup from stop mode. Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external interrupt.
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Chapter 11 Low-Voltage Inhibit (LVI) 11.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF. 11.2 Features Features of the LVI module include: • Programmable LVI reset • Selectable LVI trip voltage • Programmable stop mode operation 11.3 Functional Description Figure 11-1 shows the structure of the LVI module. The LVI is enabled out of reset.
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Low-Voltage Inhibit (LVI) LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See Figure 5-2. Configuration Register 1 (CONFIG1) for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 15.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI.
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LVI Status Register 11.3.3 Voltage Hysteresis Protection Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS. 11.3.
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Low-Voltage Inhibit (LVI) 11.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 11.6.2 Stop Mode If enabled in stop mode (LVISTOP bit in the configuration register is set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908GR16A Data Sheet, Rev. 1.
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Chapter 12 Input/Output (I/O) Ports 12.1 Introduction Bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with pullup devices if configured as input port bits. The pullup devices are automatically and dynamically disabled when a port bit is switched to output mode. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
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Input/Output (I/O) Ports Addr. $0005 $0006 $0007 $0008 $000C $000D $000E $000F Register Name Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Read: Port E Data Register (PTE) Write: See page 127.
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Introduction Table 12-1.
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Input/Output (I/O) Ports 12.2 Port A Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module. Port A also has software configurable pullup devices if configured as an input port. 12.2.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the eight port A pins.
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Port A Figure 12-4 shows the port A I/O logic. VDD PTAPUEx READ DDRA ($0004) INTERNAL PULLUP DEVICE WRITE DDRA ($0004) DDRAx INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx READ PTA ($0000) Figure 12-4. Port A I/O Circuit When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
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Input/Output (I/O) Ports 12.2.3 Port A Input Pullup Enable Register The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each of the eight port A pins. Each bit is individually configurable and requires that the data direction register, DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRA is configured for output mode.
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Port B 12.3.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer. Address: Read: Write: Reset: $0005 Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 12-7.
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Input/Output (I/O) Ports 12.4 Port C Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. 12.4.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the seven port C pins. Address: $0002 Bit 7 Read: 1 Write: 6 5 4 3 2 1 Bit 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Reset: Unaffected by reset = Unimplemented Figure 12-9.
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Port C Figure 12-11 shows the port C I/O logic. VDD PTCPUEx READ DDRC ($0006) INTERNAL PULLUP DEVICE INTERNAL DATA BUS WRITE DDRC ($0006) DDRCx RESET WRITE PTC ($0002) PTCx PTCx READ PTC ($0002) Figure 12-11. Port C I/O Circuit When bit DDRCx is a 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
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Input/Output (I/O) Ports 12.4.3 Port C Input Pullup Enable Register The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the seven port C pins. Each bit is individually configurable and requires that the data direction register, DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRC is configured for output mode.
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Port D T1CH1 and T1CH0 — Timer 1 Channel I/O Bits The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 18 Timer Interface Module (TIM1 and TIM2). SPSCK — SPI Serial Clock The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the PTD3/SPSCK pin is available for general-purpose I/O.
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Input/Output (I/O) Ports Figure 12-15 shows the port D I/O logic. VDD PTDPUEx READ DDRD ($0007) INTERNAL PULLUP DEVICE WRITE DDRD ($0007) INTERNAL DATA BUS RESET DDRDx WRITE PTD ($0003) PTDx PTDx READ PTD ($0003) Figure 12-15. Port D I/O Circuit When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
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Port E 12.5.3 Port D Input Pullup Enable Register The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each of the eight port D pins. Each bit is individually configurable and requires that the data direction register, DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRD is configured for output mode.
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Input/Output (I/O) Ports RxD — SCI Receive Data Input The PTE1/RxD pin is the receive data input for the ESCI module. When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See Chapter 14 Enhanced Serial Communications Interface (ESCI) Module. TxD — SCI Transmit Data Output The PTE0/TxD pin is the transmit data output for the ESCI module.
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Port E When bit DDREx is a 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-6 summarizes the operation of the port E pins. Table 12-6.
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Input/Output (I/O) Ports MC68HC908GR16A Data Sheet, Rev. 1.
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Chapter 13 Resets and Interrupts 13.1 Introduction Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes the microcontroller (MCU) to its startup condition. An interrupt vectors the program counter to a service routine. 13.2 Resets A reset immediately returns the MCU to a known startup condition and begins program execution from a user-defined memory location. 13.2.
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Resets and Interrupts A power-on reset: • Holds the clocks to the central processor unit (CPU) and modules inactive for an oscillator stabilization delay of 4096 CGMXCLK cycles • Drives the RST pin low during the oscillator stabilization delay • Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay • Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay • Sets the POR and LVI bits in the SIM reset status register and clears
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Resets If the stop enable bit, STOP, in the CONFIG1 register is a 0, the STOP instruction causes an illegal opcode reset. 13.2.3.5 Illegal Address Reset An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal address reset sets the ILAD bit in the SIM reset status register. A data fetch from an unmapped address does not generate a reset. 13.2.
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Resets and Interrupts MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by forced monitor mode entry. 0 = POR or read of SRSR since any reset LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by low-power supply voltage 0 = POR or read of SRSR since any reset 13.3 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event.
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Interrupts example shown in Figure 13-4, if an interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. CLI BACKGROUND ROUTINE LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 13-4. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions.
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Resets and Interrupts FROM RESET BREAK INTERRUPT ? NO YES YES BITSET? SET? IIBIT NO IRQ INTERRUPT ? NO YES CGM INTERRUPT ? NO YES OTHER INTERRUPTS ? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION ? YES NO RTI INSTRUCTION ? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 13-5. Interrupt Processing MC68HC908GR16A Data Sheet, Rev. 1.
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Interrupts Table 13-1.
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Resets and Interrupts 13.3.2.3 IRQ Pin A 0 on the IRQ pin latches an external interrupt request. 13.3.2.4 Clock Generator (CGM) The CGM can generate a CPU interrupt request every time the phase-locked loop circuit (PLL) enters or leaves the locked state. When the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the PLL bandwidth control register. PLLF is in the PLL control register. 13.3.2.
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Interrupts • Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE, enables OVRF CPU interrupt requests. OVRF and ERRIE are in the SPI status and control register. 13.3.2.
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Resets and Interrupts Interrupts must be acknowledged by writing a 1 to the TACK bit. 13.3.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 13-2 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 13-2.
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Interrupts 13.3.3.2 Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 13-7. Interrupt Status Register 2 (INT2) IF14–IF7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown in Table 13-2. 1 = Interrupt request present 0 = No interrupt request present 13.3.3.
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Resets and Interrupts MC68HC908GR16A Data Sheet, Rev. 1.
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Chapter 14 Enhanced Serial Communications Interface (ESCI) Module 14.1 Introduction The enhanced serial communications interface (ESCI) module allows asynchronous communications with peripheral devices and other microcontroller units (MCU). 14.
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Enhanced Serial Communications Interface (ESCI) Module INTERNAL BUS PORTB PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1), (2) PTC3(1), (2) PTC2(1), (2) PTC1(1), (2) PTC0(1), (2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD DDRA PORTA PTA7/KBD7– PTA0/KBD0(1) PORTC PROGRAMMABLE TIMEBASE MODULE ARITHMETIC/LOGIC UNIT (ALU) PORTD SINGLE BREAKPOINT BREAK MODULE CONT
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Functional Description 14.4 Functional Description Figure 14-2 shows the structure of the ESCI module. The ESCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the ESCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the ESCI, writes the data to be transmitted, and processes received data.
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Enhanced Serial Communications Interface (ESCI) Module The baud rate clock source for the ESCI can be selected via the configuration bit, ESCIBDSRC, of the CONFIG2 register ($001E). For reference, a summary of the ESCI module input/output registers is provided in Figure 14-3. Addr. $0009 $000A $000B Register Name ESCI Prescaler Register Read: (SCPSC) Write: See page 166. Reset: ESCI Arbiter Control Read: Register (SCIACTL) Write: See page 170.
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Functional Description 14.4.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 14-4. PARITY OR DATA BIT 8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 STOP BIT PARITY OR DATA BIT 9-BIT DATA FORMAT (BIT M IN SCC1 SET) START BIT NEXT START BIT BIT 6 BIT 7 BIT 8 NEXT START BIT STOP BIT Figure 14-4. SCI Data Formats 14.4.
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Enhanced Serial Communications Interface (ESCI) Module 14.4.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). 14.4.2.2 Character Transmission During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin.
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Functional Description • • • Clears the R8 bit in SCC3 Sets the break flag bit (BKF) in SCS2 May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits 14.4.2.4 Idle Characters For TXINV = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission.
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Enhanced Serial Communications Interface (ESCI) Module INTERNAL BUS SCP1 SCR1 SCP0 SCR0 PDS2 STOP ÷ 16 DATA RECOVERY RxD BKF CGMXCLK OR BUS CLOCK BAUD DIVIDER ALL ZEROS RPF H ALL ONES PRESCALER PRESCALER ÷4 ESCI DATA REGISTER START SCR2 11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0 L MSB LINR PDS1 PDS0 PSSB4 PSSB3 PSSB2 M WAKE ILTY PSSB1 PEN PSSB0 PTY SCRF WAKEUP LOGIC PARITY CHECKING IDLE ILIE CPU INTERRUPT REQUEST SCRF SCRIE OR ORIE NF NEIE ERROR CPU INTERRUPT RE
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Functional Description 14.4.3.2 Character Reception During an ESCI reception, the receive shift register shifts characters in from the RxD pin. The ESCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The ESCI receiver full bit, SCRF, in ESCI status register 1 (SCS1) becomes set, indicating that the received byte can be read.
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Enhanced Serial Communications Interface (ESCI) Module If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-3 summarizes the results of the data bit samples. Table 14-3.
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Functional Description error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times.
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Enhanced Serial Communications Interface (ESCI) Module STOP IDLE OR NEXT CHARACTER RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK DATA SAMPLES Figure 14-9. Fast Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
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Low-Power Modes NOTE With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle will cause the receiver to wake up. 14.4.3.7 Receiver Interrupts These sources can generate CPU interrupt requests from the ESCI receiver: • ESCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request.
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Enhanced Serial Communications Interface (ESCI) Module 14.6 ESCI During Break Module Interrupts The BCFE bit in the break flag control register (SBFCR) enables software to clear status bits during the break state. See Chapter 19 Development Support. To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.
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I/O Registers 14.8.1 ESCI Control Register 1 ESCI control register 1 (SCC1): • Enables loop mode operation • Enables the ESCI • Controls output polarity • Controls character length • Controls ESCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type Address: $0013 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 Figure 14-10.
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Enhanced Serial Communications Interface (ESCI) Module Table 14-5.
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I/O Registers • • • • Enables the transmitter Enables the receiver Enables ESCI wakeup Transmits ESCI break characters Address: $0014 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 14-11. ESCI Control Register 2 (SCC2) SCTIE — ESCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate ESCI transmitter CPU interrupt requests.
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Enhanced Serial Communications Interface (ESCI) Module RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE Writing to the RE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1.
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I/O Registers When the ESCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the ESCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset clears the T8 bit.
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Enhanced Serial Communications Interface (ESCI) Module SCTE — ESCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an ESCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an ESCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
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I/O Registers In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register.
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Enhanced Serial Communications Interface (ESCI) Module 14.8.5 ESCI Status Register 2 ESCI status register 2 (SCS2) contains flags to signal these conditions: • Break character detected • Incoming data Address: Read: $0017 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 BKF RPF 0 0 0 0 0 0 0 Write: Reset: 0 = Unimplemented Figure 14-15. ESCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the ESCI detects a break character on the RxD pin.
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I/O Registers 14.8.7 ESCI Baud Rate Register The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for both the receiver and the transmitter. NOTE There are two prescalers available to adjust the baud rate. One in the ESCI baud rate register and one in the ESCI prescaler register. Address: Read: Write: Reset: $0019 Bit 7 6 5 4 3 2 1 Bit 0 LINT LINR SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 0 0 R = Reserved Figure 14-17.
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Enhanced Serial Communications Interface (ESCI) Module node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. The break symbol length must be verified in software in any case, but the LINR bit serves as a filter, preventing false detections of break characters that are really 0x00 data characters. SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits These read/write bits select the baud rate register prescaler divisor as shown in Table 14-8.
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I/O Registers PDS2–PDS0 — Prescaler Divisor Select Bits These read/write bits select the prescaler divisor as shown in Table 14-10. Reset clears PDS2–PDS0. NOTE The setting of ‘000’ will bypass not only this prescaler but also the prescaler divisor fine adjust (PDFA). It is not recommended to bypass the prescaler while ENSCI is set, because the switching is not glitch free. Table 14-10.
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Enhanced Serial Communications Interface (ESCI) Module Table 14-11. ESCI Prescaler Divisor Fine Adjust (Continued) PSSB[4:3:2:1:0] Prescaler Divisor Fine Adjust (PDFA) 1 0 0 0 0 16/32 = 0.5 1 0 0 0 1 17/32 = 0.53125 1 0 0 1 0 18/32 = 0.5625 1 0 0 1 1 19/32 = 0.59375 1 0 1 0 0 20/32 = 0.625 1 0 1 0 1 21/32 = 0.65625 1 0 1 1 0 22/32 = 0.6875 1 0 1 1 1 23/32 = 0.71875 1 1 0 0 0 24/32 = 0.75 1 1 0 0 1 25/32 = 0.78125 1 1 0 1 0 26/32 = 0.8125 1 1 0 1 1 27/32 = 0.
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I/O Registers Table 14-12. ESCI Baud Rate Selection Examples PS[2:1:0] PSSB[4:3:2:1:0] SCP[1:0] Prescaler Divisor (BPD) SCR[2:1:0] Baud Rate Divisor (BD) 0 0 0 X X X X X 0 0 1 0 0 0 1 76,800 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 9600 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 9562.65 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 9525.58 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 8563.
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Enhanced Serial Communications Interface (ESCI) Module 14.9 ESCI Arbiter The ESCI module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time detection. The arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. The CPU can control operation mode via the ESCI arbiter control register (SCIACTL). 14.9.
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ESCI Arbiter AROVFL— Arbiter Counter Overflow Bit This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to SCIACTL. Writing 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears AROVFL. 1 = Arbiter counter overflow has occurred 0 = No arbiter counter overflow has occurred ARD8— Arbiter Counter MSB This read-only bit is the MSB of the 9-bit arbiter counter. Clear ARD8 by writing any value to SCIACTL. Reset clears ARD8. 14.9.
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Enhanced Serial Communications Interface (ESCI) Module MEASURED TIME CPU READS RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 COUNTER STARTS, ARUN = 1 CPU WRITES SCIACTL WITH $20 RXD Figure 14-21. Bit Time Measurement with ACLK = 0 MEASURED TIME CPU READS RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 CPU WRITES SCIACTL WITH $30 COUNTER STARTS, ARUN = 1 RXD Figure 14-22.
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Chapter 15 System Integration Module (SIM) 15.1 Introduction This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 15-1. Table 15-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing.
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System Integration Module (SIM) The SIM is responsible for: • Bus clock generation and control for CPU and peripherals: – Stop/wait/reset/break entry and recovery – Internal clock control • Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout • Interrupt arbitration Table 15-1 shows the internal signal names used in this section. Table 15-1.
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SIM Bus Clock Control and Generation 15.2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 15-3. This clock originates from either an external oscillator or from the on-chip PLL. 15.2.
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System Integration Module (SIM) 15.3 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • Illegal address • Forced monitor mode entry reset (MODRST) All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the internal reset signal (IRST).
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Reset and System Initialization IRST RST PULLED LOW BY MCU RST 32 CYCLES 32 CYCLES CGMXCLK IAB VECTOR HIGH Figure 15-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR MODRST INTERNAL RESET Figure 15-6. Sources of Internal Reset Table 15-2. Reset Recovery Type Reset Recovery Type Actual Number of Cycles POR/LVI 4163 (4096 + 64 + 3) All others 67 (64 + 3) 15.3.2.
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System Integration Module (SIM) OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES CGMXCLK CGMOUT RST IRST $FFFE IAB $FFFF Figure 15-7. POR Recovery 15.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources.
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SIM Counter low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 15.3.2.6 Monitor Mode Entry Module Reset (MODRST) The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is entered in the condition where the reset vectors are erased ($FF) (see 19.3.1.1 Normal Monitor Mode).
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System Integration Module (SIM) 15.5.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 15-8 shows interrupt entry timing. Figure 15-9 shows interrupt recovery timing.
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Exception Control Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). See Figure 15-10.
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System Integration Module (SIM) 15.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts.
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Exception Control 15.5.1.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 15-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 15-3.
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System Integration Module (SIM) Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: I14 I13 I12 I11 I10 I9 I8 I7 Write: R R R R R R R R 0 0 0 0 0 0 0 0 R = Reserved Reset: Figure 15-13. Interrupt Status Register 2 (INT2) I14–I7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown in Table 15-3.
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Low-Power Modes Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited.
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System Integration Module (SIM) IAB $6E0B $A6 IDB $A6 $6E0C $A6 $00FF $01 $0B $00FE $00FD $00FC $6E EXITSTOPWAIT Note: EXITSTOPWAIT = RST pin or CPU interrupt Figure 15-16. Wait Recovery from Interrupt 32 CYCLES IAB IDB $6E0B $A6 $A6 32 CYCLES RSTVCT H RSTVCTL $A6 RST CGMXCLK Figure 15-17. Wait Recovery from Internal Reset 15.6.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled.
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SIM Registers CPUSTOP IAB STOP ADDR + 1 STOP ADDR IDB PREVIOUS DATA SAME SAME NEXT OPCODE SAME SAME R/W Note: Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 15-18. Stop Mode Entry Timing STOP RECOVERY PERIOD CGMXCLK INT/BREAK IAB STOP + 2 STOP +1 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 15-19. Stop Mode Recovery from Interrupt 15.7 SIM Registers The SIM has three memory-mapped registers. Table 15-4 shows the mapping of these registers.
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System Integration Module (SIM) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt. 0 = Wait mode was not exited by break interrupt. 15.7.2 SIM Reset Status Register The SRSR register contains flags that show the source of the last reset. The status register will automatically clear after reading SRSR.
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SIM Registers 15.7.3 SIM Break Flag Control Register The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 15-22.
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System Integration Module (SIM) MC68HC908GR16A Data Sheet, Rev. 1.
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Chapter 16 Serial Peripheral Interface (SPI) Module 16.1 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. 16.
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Serial Peripheral Interface (SPI) Module INTERNAL BUS DDRA PORTA PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1), (2) PTC3(1), (2) PTC2(1), (2) PTC1(1), (2) PTC0(1), (2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD DDRB SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE USER FLASH — 15,872 BYTES PTA7/KBD7– PTA0/KBD0(1) PORTB CONTROL AND STATUS
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Functional Description INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER BUSCLK 7 6 5 4 3 2 1 MISO 0 ÷2 MOSI ÷8 CLOCK DIVIDER RECEIVE DATA REGISTER ÷ 32 PIN CONTROL LOGIC ÷ 128 SPMSTR SPE CLOCK SELECT SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR TRANSMITTER CPU INTERRUPT REQUEST CPHA CPOL MODFEN SPWOM ERRIE SPI CONTROL SPTIE RECEIVER/ERROR CPU INTERRUPT REQUEST SPRIE SPE SPRF SPTE OVRF MODF Figure 16-2. SPI Module Block Diagram Addr.
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Serial Peripheral Interface (SPI) Module 16.3.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE In a multi-SPI system, configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See 16.12.1 SPI Control Register. Only a master SPI module can initiate transmissions.
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Transmission Formats The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master.
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Serial Peripheral Interface (SPI) Module input (SS) is low, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 16.6.2 Mode Fault Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe.
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Transmission Formats pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 16.6.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line.
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Serial Peripheral Interface (SPI) Module WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 6 BIT 5 SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 1 2 3 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST LATEST WRITE TO SPDR SPSCK = BUS CLOCK ÷ 2; 2 POSSIBLE START POINTS BUS CLOCK EARLIEST WRITE TO SPDR SPSCK = BUS CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK ÷ 32; 32 POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK ÷ 128; 128 POSSIBLE ST
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Queuing Transmission Data 16.5 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when SPTE is high.
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Serial Peripheral Interface (SPI) Module 16.6 Error Conditions The following flags signal SPI error conditions: • Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register.
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Error Conditions In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. Figure 16-11 illustrates this process.
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Serial Peripheral Interface (SPI) Module In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes low. A mode fault in a master SPI causes the following events to occur: • If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. • The SPE bit is cleared. • The SPTE bit is set. • The SPI state counter is cleared. • The data direction register of the shared I/O port regains control of port drivers.
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Interrupts Table 16-1. SPI Interrupts Flag Request SPTE Transmitter empty SPI transmitter CPU interrupt request (SPTIE = 1, SPE = 1) SPRF Receiver full SPI receiver CPU interrupt request (SPRIE = 1) OVRF Overflow SPI receiver/error interrupt request (ERRIE = 1) MODF Mode fault SPI receiver/error interrupt request (ERRIE = 1) Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF.
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Serial Peripheral Interface (SPI) Module 16.8 Resetting the SPI Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is 0. Whenever SPE is 0, the following occurs: • The SPTE flag is set. • Any transmission currently in progress is aborted. • The shift register is cleared. • The SPI state counter is cleared, making it ready for a new complete transmission. • All the SPI port logic is defaulted back to being general-purpose I/O.
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I/O Signals To protect status bits during the break state, write a 0 to BCFE. With BCFE at 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is 0. After the break, doing the second step clears the status bit.
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Serial Peripheral Interface (SPI) Module When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. 16.11.4 SS (Slave Select) The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, SS is used to select a slave. For CPHA = 0, SS is used to define the start of a transmission. (See 16.4 Transmission Formats.
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I/O Registers 16.12 I/O Registers Three registers control and monitor SPI operation: • SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR) 16.12.
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Serial Peripheral Interface (SPI) Module SPE — SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 16.8 Resetting the SPI.) Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE— SPI Transmit Interrupt Enable This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
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I/O Registers OVRF — Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the receive data register. Reset clears the OVRF bit.
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Serial Peripheral Interface (SPI) Module Use this formula to calculate the SPI baud rate: Baud rate = BUSCLK BD 16.12.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values.
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Chapter 17 Timebase Module (TBM) 17.1 Introduction This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the external clock source. This TBM version uses 15 divider stages, eight of which are user selectable. A configuration option bit to select an additional 128 divide of the external clock source can be selected. See Chapter 5 Configuration Register (CONFIG) 17.
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Timebase Module (TBM) TBMCLKSEL FROM CONFIG2 CGMXCLK FROM CGM MODULE TBMCLK 0 1 DIVIDE BY 128 PRESCALER TBON ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 TACK ÷2 TBR0 ÷2 TBR1 ÷2 TBR2 TBMINT TBIF 000 TBIE R 001 010 100 SEL 011 101 110 111 Figure 17-1. Timebase Block Diagram 17.
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Low-Power Modes Table 17-1. Timebase Divider Selection Divider TBR2 TBR1 TBR0 TBMCLKSEL 0 1 0 0 0 32,768 4,194,304 0 0 1 8192 1,048,576 0 1 0 2048 262144 0 1 1 128 16,384 1 0 0 64 8192 1 0 1 32 4096 1 1 0 16 2048 1 1 1 8 1024 As an example, the divider is 16,384 with a 4.9152 MHz crystal, the TBMCLKSEL set for divide-by-128, and TBR2–TBR0 set to {011}. The interrupt period is: 16,384/4.9152 x 106 = 3.
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Timebase Module (TBM) 17.7 Timebase Control Register The timebase has one register, the timebase control register (TBCR), which is used to enable the timebase interrupts and set the rate. Address: $001C Bit 7 Read: TBIF Write: Reset: 0 6 5 4 TBR2 TBR1 TBR0 0 0 0 = Unimplemented 3 2 1 Bit 0 TBIE TBON R 0 0 0 0 R = Reserved 0 TACK Figure 17-2. Timebase Control Register (TBCR) TBIF — Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over.
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Chapter 18 Timer Interface Module (TIM1 and TIM2) 18.1 Introduction This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 18-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
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Timer Interface Module (TIM1 and TIM2) INTERNAL BUS DDRA PORTA PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1), (2) PTC3(1), (2) PTC2(1), (2) PTC1(1), (2) PTC0(1), (2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD DDRB SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE USER FLASH — 15,872 BYTES PTA7/KBD7– PTA0/KBD0(1) PORTB CONTROL AND STATUS RE
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Features 18.2 Features Features of the TIM include: • Two input capture/output compare channels: – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action • Buffered and unbuffered pulse-width-modulation (PWM) signal generation • Programmable TIM clock input with 7-frequency internal bus clock prescaler selection • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits 18.
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Timer Interface Module (TIM1 and TIM2) Addr. $0020 $0021 $0022 Register Name Bit 7 Timer 1 Status and Control Read: Register (T1SC) Write: See page 225. Reset: TOF $002B 1 Bit 0 PS2 PS1 PS0 1 0 0 0 0 0 Timer 1 Counter Read: Register High (T1CNTH) Write: See page 226. Reset: Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Timer 1 Counter Read: Register Low (T1CNTL) Write: See page 226.
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Functional Description Addr. $002C $002D $002E $002F Register Name Bit 7 6 5 4 3 2 1 Bit 0 Timer 2 Counter Read: Register High (T2CNTH) Write: See page 226. Reset: Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Timer 2 Counter Read: Register Low (T2CNTL) Write: See page 226.
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Timer Interface Module (TIM1 and TIM2) into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. 18.4.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin.
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Functional Description 18.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal.
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Timer Interface Module (TIM1 and TIM2) • When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare.
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Interrupts c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Table 18-3. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare.
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Timer Interface Module (TIM1 and TIM2) 18.6.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. 18.7 TIM During Break Interrupts A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state.
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I/O Registers Address: T1SC, $002 and T2SC, $002B Bit 7 Read: TOF Write: 0 Reset: 0 6 5 TOIE TSTOP 0 1 4 3 0 0 TRST 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 = Unimplemented Figure 18-5. TIM Status and Control Register (TSC) TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a 0 to TOF.
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Timer Interface Module (TIM1 and TIM2) Table 18-2. Prescaler Selection PS2 PS1 PS0 TIM Clock Source 0 0 0 Internal bus clock ÷ 1 0 0 1 Internal bus clock ÷ 2 0 1 0 Internal bus clock ÷ 4 0 1 1 Internal bus clock ÷ 8 1 0 0 Internal bus clock ÷ 16 1 0 1 Internal bus clock ÷ 32 1 1 0 Internal bus clock ÷ 64 1 1 1 Not available 18.9.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
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I/O Registers Address: T1MODH, $0023 and T2MODH, $002E Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 1 1 1 1 1 1 1 1 Figure 18-8. TIM Counter Modulo Register High (TMODH) Address: T1MODL, $0024 and T2MODL, $002F Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 Figure 18-9. TIM Counter Modulo Register Low (TMODL) NOTE Reset the TIM counter before writing to the TIM counter modulo registers. 18.9.
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Timer Interface Module (TIM1 and TIM2) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a 0 to CHxF.
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I/O Registers Table 18-3.
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Timer Interface Module (TIM1 and TIM2) 18.9.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read.
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Chapter 19 Development Support 19.1 Introduction This section describes the break module, the monitor module (MON), and the monitor mode entry methods. 19.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
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Development Support INTERNAL BUS DDRA PORTA PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1), (2) PTC3(1), (2) PTC2(1), (2) PTC1(1), (2) PTC0(1), (2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD DDRB SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE USER FLASH — 15,872 BYTES PTA7/KBD7– PTA0/KBD0(1) PORTB CONTROL AND STATUS REGISTERS — 64 BYTES
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Break Module (BRK) ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] BKPT (TO SIM) CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] Figure 19-2. Break Module Block Diagram Addr. $FE00 Register Name SIM Break Status Register Read: (SBSR) Write: See page 236. Reset: Read: Reserved Write: $FE02 Reset: $FE03 $FE09 SIM Break Flag Control Read: Register (SBFCR) Write: See page 236. Reset: Break Address High Read: Register (BRKH) Write: See page 235.
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Development Support When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not execute
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Break Module (BRK) 19.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: $FE0B Read: Write: Reset: Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 19-4. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit.
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Development Support 19.2.2.3 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Address: $FE00 Read: Write: Bit 7 6 5 4 3 2 R R R R R R 1 SBSW Note(1) Reset: Bit 0 R 0 R = Reserved 1. Writing a 0 clears SBSW. Figure 19-7. SIM Break Status Register (SBSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine.
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Monitor Module (MON) 19.3 Monitor Module (MON) The monitor module allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
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Development Support POR RESET NO CONDITIONS FROM Table 19-1 PTA0 = 1, PTA1 = 0, RESET VECTOR BLANK? IRQ = VTST? YES PTA0 = 1, PTA1 = 0, PTB0 = 1, AND PTB1 = 0? NO NO YES YES FORCED MONITOR MODE NORMAL USER MODE NORMAL MONITOR MODE INVALID USER MODE HOST SENDS 8 SECURITY BYTES IS RESET POR? YES NO YES ARE ALL SECURITY BYTES CORRECT? ENABLE FLASH NO DISABLE FLASH MONITOR MODE ENTRY DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) EXECUTE MONITOR CODE YES DOES RESET OCCUR? NO
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Monitor Module (MON) MC68HC908GR16A N.C. RST VDD 47 pF VDDA OSC2 MAX232 1 1 µF + 4 1 µF + 10 k 1 kΩ IRQ 3 10 k 1 µF 74HC125 3 2 9 PTA1 10 kΩ 74HC125 5 6 10 8 10 k PTB1 9.1 V DB9 7 PTB0 VDD + 2 PTB4 V– 6 5 C2– 10 k 1 µF V+ 2 C2+ + VDD OSC1 8 MHz GND 15 C1– 0.1 µF 10 MΩ 27 pF + 3 1 µF VDD VCC 16 C1+ VDD PTA0 VSSA VSS 4 1 5 Figure 19-10. Normal Monitor Mode Circuit MC68HC908GR16A N.C.
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Development Support Table 19-1.
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Monitor Module (MON) Enter monitor mode with pin configuration shown in Table 19-1 with a power-on reset. The rising edge of RST latches monitor mode. Once monitor mode is latched, the levels on the port pins except PTA0 can change. Once out of reset, the MCU waits for the host to send eight security bytes (see 19.3.2 Security). After the security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to receive a command. 19.3.1.
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Development Support Table 19-2. Mode Differences Functions Modes Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD 19.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical.
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Monitor Module (MON) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE Wait one bit time after each echo before sending the next byte.
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Development Support Table 19-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE ADDRESS HIGH WRITE ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 19-5.
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Monitor Module (MON) Table 19-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 19-8.
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Development Support 19.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
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Chapter 20 Electrical Specifications 20.1 Introduction This section contains electrical and timing specifications. 20.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 20.5 5-Vdc Electrical Characteristics and 20.6 3.3-Vdc Electrical Characteristics for guaranteed operating conditions.
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Electrical Specifications 20.3 Functional Operating Range Characteristic Symbol Value Unit TA –40 to +125 °C VDD 5.0 ±10% 3.
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5-Vdc Electrical Characteristics 20.5 5-Vdc Electrical Characteristics Typ(2) Max Unit — — — — — — V V V — 50 mA — 50 mA — 100 mA — — — — — — 0.4 1.5 1.5 V V V — — 50 mA IOL2 — — 50 mA IOLT — — 100 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.2 × VDD V — — 20 6 30 12 mA mA — — — — — 3 20 300 50 500 — — — — — µA µA µA µA µA Characteristic(1) Output high voltage (ILoad = –2.
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Electrical Specifications Symbol Min Typ(2) Max Unit Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD + 2.5 — VDD + 4.0 V Low-voltage inhibit, trip falling voltage VTRIPF 3.90 4.25 4.50 V Low-voltage inhibit, trip rising voltage VTRIPR 4.20 4.35 4.
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3.3-Vdc Electrical Characteristics 20.6 3.3-Vdc Electrical Characteristics Typ(2) Max Unit — — — — — — V V V — 30 mA — 30 mA — 60 mA — — — — — — 0.3 1.0 0.8 V V V — — 30 mA IOL2 — — 30 mA IOLT — — 60 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.3 × VDD V — — 8 3 12 6 mA mA — — — — — 2 12 200 30 300 — — — — — µA µA µA µA µA Characteristic(1) Output high voltage (ILoad = –0.
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Electrical Specifications Symbol Min Typ(2) Max Unit Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD + 2.5 — VDD + 4.0 V Low-voltage inhibit, trip falling voltage VTRIPF 2.35 2.6 2.7 V Low-voltage inhibit, trip rising voltage VTRIPR 2.4 2.66 2.
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5.0-Volt Control Timing 20.7 5.0-Volt Control Timing Symbol Min Max Unit fOSC 1 dc 8 32 MHz Internal operating frequency fOP (fBus) — 8 MHz Internal clock period (1/fOP) tCYC 125 — ns RST input pulse width low tRL 50 — ns IRQ interrupt pulse width low (edge-triggered) tILIH 50 — ns IRQ interrupt pulse period tILIL Note(3) — tCYC Characteristic(1) Frequency of operation Crystal option External clock option(2) 1.
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Electrical Specifications 20.9 Clock Generation Module (CGM) Characteristics 20.9.1 CGM Component Specifications Characteristic Symbol Min Typ Max Unit fXCLK 1 4 8 MHz Crystal load capacitance(1) CL — 20 — pF Crystal fixed capacitance C1 — (2 x CL) –5 — pF Crystal tuning capacitance C2 — (2 x CL) –5 — pF Feedback bias resistor RB 0.
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5.0-Volt ADC Characteristics 20.10 5.0-Volt ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 4.5 5.5 V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VDDAD Resolution BAD 10 10 Bits Absolute accuracy AAD –4 +4 LSB Includes quantization ADC internal clock fADIC 500 k 1.
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Electrical Specifications 20.11 3.3-Volt ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 3.0 3.6 V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VDDAD Resolution BAD 10 10 Bits Absolute accuracy AAD –6 +6 LSB Includes quantization ADC internal clock fADIC 500 k 1.
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5.0-Volt SPI Characteristics 20.12 5.
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Electrical Specifications 20.13 3.
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3.3-Volt SPI Characteristics SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT MSB IN BITS 6–1 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
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Electrical Specifications SS INPUT 3 1 SPSCK INPUT CPOL = 0 5 4 2 SPSCK INPUT CPOL = 1 5 4 9 8 MISO INPUT SLAVE MSB OUT 6 MOSI OUTPUT BITS 6–1 7 NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT CPOL = 0 5 4 2 3 SPSCK INPUT CPOL = 1 8 MISO OUTPUT MOSI INPUT 5 4 10 NOTE 9 SLAVE MSB OUT 6 7 BITS 6–1 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defi
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Timer Interface Module Characteristics 20.14 Timer Interface Module Characteristics Characteristic Symbol Timer input capture pulse width Timer Input capture period Min Max Unit tTH, tTL 2 — tCYC tTLTL Note(1) — tCYC 1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC. tTLTL tTH INPUT CAPTURE RISING EDGE tTLTL tTL INPUT CAPTURE FALLING EDGE tTLTL tTH tTL INPUT CAPTURE BOTH EDGES Figure 20-4.
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Electrical Specifications 20.15 Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz fRead(1) 0 — 8M Hz tErase 0.9 3.6 1 4 1.1 5.
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Chapter 21 Ordering Information and Mechanical Specifications 21.1 Introduction This section provides ordering information for the MC68HC908GR16A along with the dimensions for: • 32-pin low-profile quad flat pack package (case 873A) • 48-pin low-profile quad flat pack (case 932-03) The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Semiconductor Sales Office. 21.
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