Datasheet

Exception Control
MC68HC908GR16A Data Sheet, Rev. 1.0
Freescale Semiconductor 183
15.5.1.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources.
Table 15-3 summarizes the interrupt sources and the interrupt status register flags that they set. The
interrupt status registers can be useful for debugging.
Interrupt Status Register 1
I6–I1 — Interrupt Flags 1–6
These flags indicate the presence of interrupt requests from the sources shown in Table 15-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
Table 15-3. Interrupt Sources
Priority Interrupt Source
Interrupt Status
Register Flag
Highest Reset —
SWI instruction —
IRQ
pin I1
CGM clock monitor I2
TIM1 channel 0 I3
TIM1 channel 1 I4
TIM1 overflow I5
TIM2 channel 0 I6
TIM2 channel 1 I7
TIM2 overflow I8
SPI receiver full I9
SPI transmitter empty I10
SCI receive error I11
SCI receive I12
SCI transmit I13
Keyboard I14
ADC conversion complete I15
Lowest Timebase module I16
Address: $FE04
Bit 7654321Bit 0
Read:I6I5I4I3I2I1 0 0
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 15-12. Interrupt Status Register 1 (INT1)