Datasheet

Clock Generator Module (CGM)
MC68HC908GR16A Data Sheet, Rev. 1.0
66 Freescale Semiconductor
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at start up.
4.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
4.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL) — See 4.5.1 PLL Control Register
• PLL bandwidth control register (PBWC) — see 4.5.2 PLL Bandwidth Control Register
• PLL multiplier select register high (PMSH) — see 4.5.3 PLL Multiplier Select Register High
• PLL multiplier select register low (PMSL) — see 4.5.4 PLL Multiplier Select Register Low
• PLL VCO range select register (PMRS) — see 4.5.5 PLL VCO Range Select Register
Figure 4-3 is a summary of the CGM registers.
Addr.Register Name Bit 7654321Bit 0
$0036
PLL Control Register
(PCTL)
See page 67.
Read:
PLLIE
PLLF
PLLON BCS R R VPR1 VPR0
Write:
Reset:00100000
$0037
PLL Bandwidth Control
Register (PBWC)
See page 68.
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:00000000
$0038
PLL Multiplier Select High
Register (PMSH)
See page 69.
Read:0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
$0039
PLL Multiplier Select Low
Register (PMSL)
See page 70.
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
$003A
PLL VCO Select Range
Register (PMRS)
See page 70.
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
$003B Reserved Register
Read:0000
RRRR
Write:
Reset:00000001
= Unimplemented R = Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ
is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 4-3. CGM I/O Register Summary