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M68HC08

Microcontrollers

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MC68HC908GR16

Data Sheet

MC68HC908GR16

Rev. 5.0

04/2007

Summary of content (276 pages)

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MC68HC908GR16 Data Sheet M68HC08 Microcontrollers MC68HC908GR16 Rev. 5.0 04/2007 freescale.
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MC68HC908GR16 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
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Revision History Revision History (Continued) Date September, 2004 March, 2005 January, 2007 April, 2007 Revision Level 2.0 3.0 4.0 5.o Page Number(s) Description Figure 1-1. MCU Block Diagram — Removed data bus switch module 22 Figure 2-2. Control, Status, and Data Registers and Figure 5-1. Configuration Register 2 (CONFIG2) — Changed name of bit 0 from SCIBDSRC to ESCIBDSRC 29 and 78 14.8.8 ESCI Prescaler Register — Updated description in this subsection 168 14.9.
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List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Chapters MC68HC908GR16 Data Sheet, Rev. 5.
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Table of Contents Chapter 1 General Description 1.1 1.2 1.2.1 1.2.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Features of the MC68HC908GR16 . . . . . . . . . . . . . . . . .
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Table of Contents Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.
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4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 4.4.10 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.6 4.7 4.7.1 4.7.2 4.7.3 4.8 4.8.1 4.8.2 4.8.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 6.3.8 6.4 6.5 6.6 6.7 6.7.1 6.7.2 6.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . .
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9.5.2 9.6 9.7 9.7.1 9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 10.13 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.13.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.14 Exiting Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 13 Resets and Interrupts 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 External Reset . . . . . . . . . . . .
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Table of Contents 14.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.
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Table of Contents 16.12.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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18.9.3 18.9.4 18.9.5 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Chapter 19 Development Support 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 20.12 20.13 20.14 20.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 General Description 1.1 Introduction The MC68HC908GR16 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 1.2 Features For convenience, features have been organized to reflect: • Standard features of the MC68HC908GR16 • Features of the CPU08 1.2.
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General Description • • • • • • • • • • • • • • • • • • • • 1 Kbyte of on-chip random-access memory (RAM) 406 bytes of FLASH programming routines read-only memory (ROM) Serial peripheral interface (SPI) module Enhanced serial communications interface (ESCI) module LIN specific enhanced features: – Generation of LIN 1.
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MCU Block Diagram 1.2.2 Features of the CPU08 Features of the CPU08 include: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.
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General Description INTERNAL BUS CLOCK GENERATOR MODULE IRQ(3) VDDAD/VREFH VSSAD/VREFL DDRA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE DDRD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE 32–100 kHz OSCILLATOR SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE MEMORY MAP MODULE POWER-ON RE
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OSC2 CGMXFC VSSA VDDA PTC1/CANRX PTC0/CANTX PTA3/KBD3 29 28 27 26 25 1 30 RST 31 32 OSC1 Pin Assignments 24 PTA2/KBD2 PTD2/MOSI 7 18 PTB4/AD4 PTD3/SPSCK 8 17 PTB3/AD3 16 PTB5/AD5 PTB2/AD2 19 15 6 PTB1/AD1 PTD1/MISO 14 VDDAD/VREFH PTB0/AD0 20 13 5 PTD6/T2CH0 VSSAD/VREFL PTD0/SS 12 PTA0/KBD0 21 PTD5/T1CH1 22 4 PTD4/T1CH0 3 IRQ 11 PTE1/RxD 10 PTA1/KBD1 VDD 23 9 2 VSS PTE0/TxD CGMXFC VSSA VDDA PTC1/CANRX PTC0/CANTX PTA7/KBD7 PTA6/KBD6 PTA5/K
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General Description 1.5 Pin Functions Descriptions of the pin functions are provided here. 1.5.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4 shows. Place the C1 bypass capacitor as close to the MCU as possible.
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Pin Functions 1.5.5 CGM Power Supply Pins (VDDA and VSSA) VDDA and VSSA are the power supply pins for the analog portion of the clock generator module (CGM). Decoupling of these pins should be as per the digital supply. See Chapter 4 Clock Generator Module (CGM). 1.5.6 External Filter Capacitor Pin (VCGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Chapter 4 Clock Generator Module (CGM). 1.5.
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General Description 1.5.12 Port E I/O Pins (PTE5–PTE2 and PTE0/TxD) PTE5–PTE0 are general-purpose, bidirectional I/O port pins. PTE1 and PTE0 can also be programmed to be enhanced serial communications interface (ESCI) pins. See Chapter 14 Enhanced Serial Communications Interface (ESCI) Module and Chapter 12 Input/Output Ports (PORTS). NOTE Any unused inputs and I/O ports should be tied to an appropriate logic level (either VDD or VSS).
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Chapter 2 Memory 2.1 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 15,872 bytes of user FLASH memory • 1024 bytes of random-access memory (RAM) • 406 bytes of FLASH programming routines read-only memory (ROM) • 44 bytes of user-defined vectors • 350 bytes of monitor ROM 2.2 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset.
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Memory Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
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Input/Output (I/O) Section $FE10 UNIMPLEMENTED 16 BYTES RESERVED FOR COMPATIBILITY WITH MONITOR CODE FOR A-FAMILY PART ↓ $FE1F $FE20 MONITOR ROM 350 BYTES ↓ $FF7D $FF7E FLASH BLOCK PROTECT REGISTER (FLBPR) $FF7F UNIMPLEMENTED 85 BYTES ↓ $FFD3 $FFD4 FLASH VECTORS 44 BYTES ↓ $FFFF(1) 1. $FFF6–$FFFD used for eight security bytes Figure 2-1. Memory Map (Continued) Addr. Register Name $0000 Port A Data Register Read: (PTA) Write: See page 124.
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Memory Addr. $0006 $0007 $0008 $0009 Register Name Data Direction Register C Read: (DDRC) Write: See page 128. Reset: Data Direction Register D Read: (DDRD) Write: See page 131. Reset: Port E Data Register Read: (PTE) Write: See page 133. Reset: ESCI Prescaler Register Read: (SCPSC) Write: See page 170. Reset: ESCI Arbiter Control Register Read: $000A (SCIACTL) Write: See page 174. Reset: $000B $000C ESCI Arbiter Data Read: Register (SCIADAT) Write: See page 175.
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Input/Output (I/O) Section Addr. $0012 $0013 $0014 Register Name SPI Data Register Read: (SPDR) Write: See page 215. Reset: ESCI Control Register 1 Read: (SCC1) Write: See page 161. Reset: ESCI Control Register 2 Read: (SCC2) Write: See page 163.
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Memory Addr. $001E $001F Register Name Configuration Register 2 Read: (CONFIG2)(1) Write: See page 80. Reset: Configuration Register 1 Read: (CONFIG1)(1) Write: See page 80. Reset: Bit 7 6 5 4 0 0 0 0 3 0 0 0 0 0 0 0 1 COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 (Note 1) SSREC STOP COPD 0 0 0 0 0 0 0 0 PS2 PS1 PS0 R 2 1 TMBCLK- OSCENINSEL STOP Bit 0 ESCIBDSRC 1. One-time writable register after each reset, except LVI5OR3 bit.
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Input/Output (I/O) Section Addr. $0029 $002A Register Name Timer 1 Channel 1 Read: Register High (T1CH1H) Write: See page 236. Reset: Timer 1 Channel 1 Read: Register Low (T1CH1L) Write: See page 236. Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 2 1 Bit 0 PS2 PS1 PS0 Indeterminate after reset Bit 7 6 5 4 3 Indeterminate after reset Timer 2 Status and Control Read: Register (T2SC) Write: See page 231.
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Memory Addr. $0035 $0036 $0037 Register Name Timer 2 Channel 1 Read: Register Low (T2CH1L) Write: See page 236. Reset: PLL Control Register Read: (PCTL) Write: See page 70. Reset: PLL Bandwidth Control Read: Register (PBWC) Write: See page 72.
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Input/Output (I/O) Section Addr. Bit 7 6 5 4 3 2 1 Bit 0 POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 BCFE R R R R R R R 0 0 0 0 0 0 0 0 IF6 IF5 IF4 IF3 IF2 IF1 0 0 $FE04 Interrupt Status Register 1 Read: (INT1) Write: See page 145.
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Memory Addr. $FF7E Register Name FLASH Block Protect Read: Register (FLBPR)(3) Write: See page 44. Reset: Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Unaffected by reset 3. Non-volatile FLASH register $FFFF COP Control Register Read: (COPCTL) Write: See page 85. Reset: Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-2.
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Input/Output (I/O) Section Table 2-1.
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Memory 2.5 Random-Access Memory (RAM) Addresses $0040 through $043F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code.
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FLASH Memory (FLASH) Programming tools are available from Freescale Semiconductor. Contact your local representative for more information. NOTE A security feature prevents viewing of the FLASH contents.(1) 2.6.1.1 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 = Unimplemented Figure 2-3.
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Memory 2.6.1.2 FLASH Page Erase Operation Use this step-by-step procedure to erase a page (64 bytes) of FLASH memory to read as a 1. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 44-byte user interrupt vectors area also forms a page. Any FLASH memory page can be erased alone. 1. Set the ERASE bit, and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3.
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FLASH Memory (FLASH) 2.6.1.3 FLASH Mass Erase Operation Use this step-by-step procedure to erase entire FLASH memory to read as a 1: 1. Set both the ERASE bit, and the MASS bit in the FLASH control register. 2. Read from the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS (minimum 10 μs) 5. Set the HVEN bit. 6. Wait for a time, tMErase (minimum 4 ms) 7. Clear the ERASE and MASS bits. 8.
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Memory 8. 9. 10. 11. 12. 13. Wait for a time, tPROG (minimum 30 μs). Repeat step 7 and 8 until all desired bytes within the row are programmed. Clear the PGM bit.(1) Wait for a time, tNVH (minimum 5 μs). Clear the HVEN bit. After time, tRCV (typical 1 μs), the memory can be accessed in read mode again. NOTE The COP register at location $FFFF should not be written between steps 5-12, when the HVEN bit is set.
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FLASH Memory (FLASH) Algorithm for programming a row (32 bytes) of FLASH memory 1 2 3 SET PGM BIT READ THE FLASH BLOCK PROTECT REGISTER WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 5 6 7 8 WAIT FOR A TIME, tNVS SET HVEN BIT WAIT FOR A TIME, tPGS WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME, tPROG COMPLETED PROGRAMMING THIS ROW? Y N 10 11 CLEAR PGM BIT WAIT FOR A TIME, tNVH Note: The time between each FLASH address change (step 7 to st
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Memory 2.6.1.5 FLASH Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting a block of memory from unintentional erase or program operations due to system malfunction. This protection is done by using of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected.
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FLASH Memory (FLASH) 16-BIT MEMORY ADDRESS START ADDRESS OF FLASH 1 BLOCK PROTECT 1 FLBPR VALUE 0 0 0 0 0 0 Figure 2-6. FLASH Block Protect Start Address Table 2-2. Examples of Protect Address Ranges BPR[7:0] Addresses of Protect Range $00 The entire FLASH memory is protected.
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Memory MC68HC908GR16 Data Sheet, Rev. 5.
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Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the 10-bit analog-to-digital converter (ADC). 3.2 Features Features of the ADC module include: • Eight channels with multiplexed input • Linear successive approximation with monotonicity • 10-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock • Left or right justified result • Left justified sign data mode 3.
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Analog-to-Digital Converter (ADC) INTERNAL BUS CLOCK GENERATOR MODULE IRQ(3) VDDAD/VREFH VSSAD/VREFL DDRA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE DDRD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE 32–100 kHz OSCILLATOR SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE MEMORY MAP MODUL
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Functional Description INTERNAL DATA BUS READ DDRBx WRITE DDRBx DISABLE DDRBx RESET WRITE PTBx PTBx PTBx ADC CHANNEL x READ PTBx DISABLE ADC DATA REGISTER INTERRUPT LOGIC AIEN CONVERSION COMPLETE ADC ADC VOLTAGE IN (VADIN) CHANNEL SELECT ADCH4–ADCH0 ADC CLOCK COCO CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV2–ADIV0 ADICLK Figure 3-2. ADC Block Diagram 3.3.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $3FF (full scale).
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Analog-to-Digital Converter (ADC) 3.3.3 Conversion Time Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency. Conversion time = 16 to 17 ADC cycles ADC frequency Number of bus cycles = conversion time × bus frequency 3.3.4 Conversion In continuous conversion mode, the ADC data register will be filled with new data after each conversion.
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Monotonicity is used when compatibility with 8-bit ADC designs are required. No interlocking between ADRH and ADRL is present. NOTE Quantization error is affected when only the most significant eight bits are used as a result. See Figure 3-3.
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Analog-to-Digital Converter (ADC) 3.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the WAIT instruction. 3.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
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I/O Registers 3.7.4 ADC Voltage Reference Low Pin (VREFL) The ADC analog portion uses VREFL as its lower voltage reference pin. By default, connect the VREFL pin to the same voltage potential as VSS. External filtering is often necessary to ensure a clean VREFL for good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values.
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Analog-to-Digital Converter (ADC) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion.
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I/O Registers 3.8.2 ADC Data Register High and Data Register Low 3.8.2.1 Left Justified Mode In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
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Analog-to-Digital Converter (ADC) 3.8.2.3 Left Justified Signed Data Mode In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read.
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I/O Registers 3.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. Address: Read: Write: Reset: $003F Bit 7 6 5 4 3 2 1 ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 R 0 0 0 0 0 1 0 R = Reserved = Unimplemented Bit 0 0 0 Figure 3-9. ADC Clock Register (ADCLK) ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock.
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Analog-to-Digital Converter (ADC) MC68HC908GR16 Data Sheet, Rev. 5.
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Chapter 4 Clock Generator Module (CGM) 4.1 Introduction This section describes the clock generator module. The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
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Clock Generator Module (CGM) OSCILLATOR (OSC) OSC2 CGMXCLK (TO: SIM, TIMEBASE, ADC) OSC1 SIMOSCEN (FROM SIM) OSCSTOPENB (FROM CONFIG) PHASE-LOCKED LOOP (PLL) CGMRDV REFERENCE DIVIDER CGMRCLK CLOCK SELECT CIRCUIT BCS RDS3–RDS0 VDDA CGMXFC ÷2 CGMOUT (TO SIM) VSSA VPR1–VPR0 VRS7–VRS0 PHASE DETECTOR VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER CGMVCLK PLL ANALOG LOCK DETECTOR LOCK CGMVDV AUTOMATIC MODE CONTROL AUTO ACQ INTERRUPT CONTROL PLLIE MUL11–MUL0 PRE1–PRE0 FREQUENCY DIVIDER FREQU
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Functional Description 4.3.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency.
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Clock Generator Module (CGM) The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, described in 4.3.4 Acquisition and Tracking Modes.
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Functional Description • • The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 4.8 Acquisition/Lock Time Specifications for more information.) CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling the LOCK bit. (See 4.5.1 PLL Control Register.) The PLL also may operate in manual mode (AUTO = 0).
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Clock Generator Module (CGM) When the tolerance on the bus frequency is tight, choose fRCLK to an integer divisor of fBUSDES, and R = 1. If fRCLK cannot meet this requirement, use the following equation to solve for R with practical choices of fRCLK, and choose the fRCLK that gives the lowest R. ⎛ f VCLKDES⎞ ⎫ ⎧ ⎛ f VCLKDES⎞ R = round R MAX × ⎨ ⎜ --------------------------⎟ – integer ⎜ --------------------------⎟ ⎬ ⎝ f RCLK ⎠ ⎭ ⎩ ⎝ f RCLK ⎠ 4. Select a VCO frequency multiplier, N.
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Functional Description 9. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS. The center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL. E f VRS = ( L × 2 )f NOM For proper operation, E f NOM × 2 f VRS – f VCLK ≤ -------------------------2 10. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS and fVCLKDES.
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Clock Generator Module (CGM) 4.3.7 Special Programming Exceptions The programming method described in 4.3.6 Programming the PLL does not account for three possible exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for these exceptions: • A 0 value for R or N is interpreted exactly the same as a value of 1. • A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See 4.3.8 Base Clock Selector Circuit. 4.3.
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I/O Signals SIMOSCEN OSCSTOPENB (FROM CONFIG) CGMXCLK OSC1 CGMXFC OSC2 VSSA VDDA VDD RB RS RF1 CF2 CBYP CF1 X1 C1 C2 Note: Filter network in box can be replaced with a single capacitor, but will degrade stability. Figure 4-2. CGM External Connections 4.4 I/O Signals The following paragraphs describe the CGM I/O signals. 4.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 4.4.
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Clock Generator Module (CGM) 4.4.4 PLL Analog Power Pin (VDDA) VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage potential as the VDD pin. NOTE Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 4.4.5 PLL Analog Ground Pin (VSSA) VSSA is a ground pin used by the analog portions of the PLL. Connect the VSSA pin to the same voltage potential as the VSS pin.
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CGM Registers 4.5 CGM Registers These registers control and monitor operation of the CGM: • PLL control register (PCTL) — see 4.5.1 PLL Control Register. • PLL bandwidth control register (PBWC) — see 4.5.2 PLL Bandwidth Control Register. • PLL multiplier select register high (PMSH) — see 4.5.3 PLL Multiplier Select Register High. • PLL multiplier select register low (PMSL) — see 4.5.4 PLL Multiplier Select Register Low. • PLL VCO range select register (PMRS) — see 4.5.5 PLL VCO Range Select Register.
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Clock Generator Module (CGM) 4.5.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: Write: Reset: PLLIE 0 6 PLLF 5 4 3 2 1 Bit 0 PLLON BCS PRE1 PRE0 VPR1 VPR0 1 0 0 0 0 0 0 = Unimplemented Figure 4-4.
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CGM Registers if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See 4.3.8 Base Clock Selector Circuit.) PRE1 and PRE0 — Prescaler Program Bits These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.
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Clock Generator Module (CGM) 4.5.
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CGM Registers 4.5.3 PLL Multiplier Select Register High The PLL multiplier select register high (PMSH) contains the programming information for the high byte of the modulo feedback divider. Address: Read: $0038 Bit 7 6 5 4 0 0 0 0 0 0 0 Write: Reset: 0 3 2 1 Bit 0 MUL11 MUL10 MUL9 MUL8 0 0 0 0 = Unimplemented Figure 4-6.
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Clock Generator Module (CGM) 4.5.5 PLL VCO Range Select Register NOTE PMRS may be called PVRS on other HC08 derivatives. The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO. Address: Read: Write: Reset: $003A Bit 7 6 5 4 3 2 1 Bit 0 VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 0 1 0 0 0 0 0 0 Figure 4-8.
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Interrupts RDS3–RDS0 — Reference Divider Select Bits These read/write bits control the modulo reference divider that selects the reference division factor, R. (See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) RDS7–RDS0 cannot be written when the PLLON bit in the PCTL is set. A value of $00 in the reference divider select register configures the reference divider the same as a value of $01. (See 4.3.7 Special Programming Exceptions.
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Clock Generator Module (CGM) 4.7.2 Stop Mode If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two driving CGMOUT, the PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal clock, CGMXCLK, divided by two as the source of CGMOUT.
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Acquisition/Lock Time Specifications 4.8.2 Parametric Influences on Reaction Time Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV.
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Clock Generator Module (CGM) CGMXFC CGMXFC RF1 CF2 CF CF1 VSSA VSSA (A) (B) Figure 4-10. PLL Filter Table 4-4. Example Filter Component Values fRCLK CF1 CF2 RF1 CF 32 kHz 0.15 μF 15 nF 2K 0.22 μF 40 kHz 0.12 μF 12 nF 2K 0.18 μF 50 kHz 0.10 μF 10 nF 2K 0.18 μF 60 kHz 82 nF 8.2 nF 2K 0.12 μF 70 kHz 68 nF 6.8 nF 2K 0.12 μF 80 kHz 56 nF 5.6 nF 2K 0.1 μF 90 kHz 56 nF 5.6 nF 2K 0.1 μF 100 kHz 47 nF 4.7 nF 2K 82 nF MC68HC908GR16 Data Sheet, Rev. 5.
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Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2.
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Configuration Register (CONFIG) Address: Read: $001E Bit 7 6 5 4 0 0 0 0 3 2 1 Bit 0 R TMBCLKSEL OSCENINSTOP ESCIBDSRC 0 0 0 0 0 0 0 1 R = Reserved Write: Reset: = Unimplemented Figure 5-1. Configuration Register 2 (CONFIG2) Address: Read: Write: Reset: $001F Bit 7 6 5 4 3 2 1 Bit 0 COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD 0 0 0 0 See note 0 0 0 Note: LVI5OR3 bit is only reset via POR (power-on reset) Figure 5-2.
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Functional Description LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. See Chapter 11 Low-Voltage Inhibit (LVI). 1 = LVI module resets disabled 0 = LVI module resets enabled LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. See Chapter 11 Low-Voltage Inhibit (LVI).
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Configuration Register (CONFIG) MC68HC908GR16 Data Sheet, Rev. 5.
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Chapter 6 Computer Operating Properly (COP) Module 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register. 6.2 Functional Description Figure 6-1 shows the structure of the COP module.
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Computer Operating Properly (COP) Module The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 8176 CGMXCLK cycle overflow option, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms.
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COP Control Register 6.3.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Chapter 5 Configuration Register (CONFIG). 6.3.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See Chapter 5 Configuration Register (CONFIG). 6.4 COP Control Register The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector.
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Computer Operating Properly (COP) Module To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt when VTST is present on the RST pin. MC68HC908GR16 Data Sheet, Rev. 5.
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Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.
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Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
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CPU Registers 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
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Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6.
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Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
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Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set.
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Instruction Set Summary Effect on CCR V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Description Operand Operation Opcode Source Form Address Mode Table
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Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP V H I N Z C Clear Compare A with M COM opr COMA COMX COM opr,X COM ,X COM opr,SP Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement DIV Divide INC opr INCA
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Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:
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Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
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Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
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MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
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Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 8.2 Features Features of the IRQ module include: • A dedicated external interrupt pin (IRQ) • IRQ interrupt control bits • Hysteresis buffer • Programmable edge-only or edge and level interrupt sensitivity • Automatic interrupt acknowledge • Internal pullup resistor 8.
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External Interrupt (IRQ) INTERNAL BUS CLOCK GENERATOR MODULE IRQ(3) VDDAD/VREFH VSSAD/VREFL DDRA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE DDRD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE 32–100 kHz OSCILLATOR SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE MEMORY MAP MODULE POWER-
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Functional Description RESET ACK TO CPU FOR BIL/BIH INSTRUCTIONS INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF D CLR Q IRQ INTERRUPT REQUEST SYNCHRONIZER CK IRQ IMASK MODE TO MODE SELECT LOGIC HIGH VOLTAGE DETECT Figure 8-2.
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External Interrupt (IRQ) 8.4 IRQ Pin A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. • If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
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IRQ Status and Control Register 8.6 IRQ Status and Control Register The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin. Address: $001D Bit 7 6 5 4 Read: 3 2 IRQF 0 Write: Reset: ACK 0 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 = Unimplemented Figure 8-4.
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External Interrupt (IRQ) MC68HC908GR16 Data Sheet, Rev. 5.
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Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup device is also enabled on the pin. 9.
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Keyboard Interrupt Module (KBI) INTERNAL BUS CLOCK GENERATOR MODULE IRQ(3) VDDAD/VREFH VSSAD/VREFL DDRA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE DDRD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE 32–100 kHz OSCILLATOR SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE MEMORY MAP MODULE
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Functional Description INTERNAL BUS VECTOR FETCH DECODER ACKK RESET KBD0 VDD . TO PULLUP ENABLE KB0IE KEYF D . CLR Q SYNCHRONIZER CK . KEYBOARD INTERRUPT REQUEST IMASKK KBD7 MODEK TO PULLUP ENABLE KB7IE Figure 9-2. Keyboard Module Block Diagram Addr. $001A $001B Register Name Keyboard Status Read: and Control Register Write: (INTKBSCR) See page 109. Reset: Keyboard Interrupt Enable Read: Register Write: (INTKBIER) See page 110.
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Keyboard Interrupt Module (KBI) The vector fetch or software clear and the return of all enabled keyboard interrupt pins to 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at 0.
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Keyboard Module During Break Interrupts 9.5.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 9.6 Keyboard Module During Break Interrupts The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state.
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Keyboard Interrupt Module (KBI) ACKK — Keyboard Acknowledge Bit Writing a 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as 0. Reset clears ACKK. IMASKK — Keyboard Interrupt Mask Bit Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit.
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Chapter 10 Low-Power Modes 10.1 Introduction The microcontroller (MCU) may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution. This section describes how each module acts in the low-power modes. 10.1.1 Wait Mode The WAIT instruction puts the MCU in a low-power standby mode in which the central processor unit (CPU) clock is disabled but the bus clock continues to run.
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Low-Power Modes 10.3 Break Module (BRK) 10.3.1 Wait Mode If enabled, the break (BRK) module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the break status register is set. 10.3.2 Stop Mode The break module is inactive in stop mode. A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. The STOP instruction does not affect break module register states. 10.
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Computer Operating Properly Module (COP) 10.6 Computer Operating Properly Module (COP) 10.6.1 Wait Mode The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout. 10.6.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the CONFIG1 register enables the STOP instruction.
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Low-Power Modes 10.9.2 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. 10.10 Enhanced Serial Communications Interface Module (ESCI) 10.10.1 Wait Mode The enhanced serial communications interface (ESCI), or SCI module for short, module remains active in wait mode. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode.
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Timebase Module (TBM) 10.12.2 Stop Mode The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. 10.13 Timebase Module (TBM) 10.13.1 Wait Mode The timebase module (TBM) remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU.
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Low-Power Modes • • • • • Timer 2 interface (TIM2) module interrupt — A CPU interrupt request from the TIM2 loads the program counter with the contents of: – $FFEC and $FFED; TIM2 overflow – $FFF0 and $FFF1; TIM2 channel 0 Serial peripheral interface (SPI) module interrupt — A CPU interrupt request from the SPI loads the program counter with the contents of: – $FFE8 and $FFE9; SPI transmitter – $FFEA and $FFEB; SPI receiver Serial communications interface (SCI) module interrupt — A CPU interrupt reques
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Chapter 11 Low-Voltage Inhibit (LVI) 11.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF. 11.2 Features Features of the LVI module include: • Programmable LVI reset • Selectable LVI trip voltage • Programmable stop mode operation 11.3 Functional Description Figure 11-1 shows the structure of the LVI module. The LVI is enabled out of reset.
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Low-Voltage Inhibit (LVI) LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See Figure 5-2. Configuration Register 1 (CONFIG1) for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 15.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI.
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LVI Status Register 11.3.3 Voltage Hysteresis Protection Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS. 11.3.
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Low-Voltage Inhibit (LVI) 11.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 11.6.2 Stop Mode If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908GR16 Data Sheet, Rev. 5.
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Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction Bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with pullup devices if configured as input port bits. The pullup devices are automatically and dynamically disabled when a port bit is switched to output mode. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
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Input/Output Ports (PORTS) Addr. $0005 $0006 $0007 $0008 $000C $000D $000E $000F Register Name Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Read: Port E Data Register (PTE) Write: See page 133.
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Introduction Table 12-1.
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Input/Output Ports (PORTS) 12.2 Port A Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module. Port A also has software configurable pullup devices if configured as an input port. 12.2.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the eight port A pins.
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Port A READ DDRA ($0004) WRITE DDRA ($0004) DDRAx INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx VDD PTAPUEx INTERNAL PULLUP DEVICE READ PTA ($0000) Figure 12-4. Port A I/O Circuit When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-2 summarizes the operation of the port A pins. Table 12-2.
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Input/Output Ports (PORTS) 12.3 Port B Port B is an 8-bit special-function port that shares six of its pins with the analog-to-digital converter (ADC) module. 12.3.1 Port B Data Register The port B data register (PTB) contains a data latch for each of the eight port pins. Address: Read: Write: $0001 Bit 7 6 5 4 3 2 1 Bit 0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 AD2 AD1 AD0 Reset: Alternative Function: Unaffected by reset AD7 AD6 AD5 AD4 AD3 Figure 12-6.
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Port B DDRB7–DDRB0 — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB7–DDRB0, configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 12-8 shows the port B I/O logic.
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Input/Output Ports (PORTS) 12.4 Port C Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. 12.4.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the port C pins. Address: $0002 Bit 7 Read: 0 Write: 6 5 4 3 2 1 Bit 0 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Reset: Unaffected by reset = Unimplemented R = Reserved Figure 12-9.
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Port C READ DDRC ($0006) INTERNAL DATA BUS WRITE DDRC ($0006) DDRCx RESET WRITE PTC ($0002) PTCx PTCx VDD PTCPUEx INTERNAL PULLUP DEVICE READ PTC ($0002) Figure 12-11. Port C I/O Circuit When bit DDRCx is a 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port C pins. Table 12-4.
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Input/Output Ports (PORTS) PTCPUE1 and PTCPUE0 — Port C Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port C pin configured to have internal pullup 0 = Corresponding port C pin internal pullup disconnected 12.5 Port D Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI) module and three of its pins with two timer interface (TIM1 and TIM2) modules.
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Port D Data direction register D (DDRD) does not affect the data direction of port D pins that are being used by the SPI module. However, the DDRD bits always determine whether reading port D returns the states of the latches or the states of the pins. See Table 12-5. SS — Slave Select The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O.
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Input/Output Ports (PORTS) When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-5 summarizes the operation of the port D pins. Table 12-5.
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Port E 12.6 Port E Port E is a 6-bit special-function port that shares two of its pins with the enhanced serial communications interface (ESCI) module. 12.6.1 Port E Data Register The port E data register contains a data latch for each of the six port E pins. Address: Read: Write: $0008 Bit 7 6 0 0 5 4 3 2 1 Bit 0 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 RxD TxD Reset: Unaffected by reset Alternative Function: = Unimplemented Figure 12-17.
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Input/Output Ports (PORTS) 12.6.2 Data Direction Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer. Address: Read: $000C Bit 7 6 0 0 0 0 Write: Reset: 5 4 3 2 1 Bit 0 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 0 = Unimplemented Figure 12-18.
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Chapter 13 Resets and Interrupts 13.1 Introduction Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes the microcontroller (MCU) to its startup condition. An interrupt vectors the program counter to a service routine. 13.2 Resets A reset immediately returns the MCU to a known startup condition and begins program execution from a user-defined memory location. 13.2.
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Resets and Interrupts A power-on reset: • Holds the clocks to the central processor unit (CPU) and modules inactive for an oscillator stabilization delay of 4096 CGMXCLK cycles • Drives the RST pin low during the oscillator stabilization delay • Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay • Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay • Sets the POR and LVI bits in the SIM reset status register and clears
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Resets 13.2.3.4 Illegal Opcode Reset An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal opcode reset sets the ILOP bit in the SIM reset status register. If the stop enable bit, STOP, in the mask option register is a 0, the STOP instruction causes an illegal opcode reset. 13.2.3.5 Illegal Address Reset An illegal address reset is an internal reset caused by opcode fetch from an unmapped address.
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Resets and Interrupts ILAD — Illegal Address Reset Bit 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR since any reset MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by forced monitor mode entry. 0 = POR or read of SRSR since any reset LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by low-power supply voltage 0 = POR or read of SRSR since any reset 13.
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Interrupts After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the example shown in Figure 13-4, if an interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
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Resets and Interrupts FROM RESET BREAK INTERRUPT ? NO YES YES BITSET? SET? IIBIT NO IRQ INTERRUPT ? NO YES CGM INTERRUPT ? NO YES OTHER INTERRUPTS ? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION ? YES NO RTI INSTRUCTION ? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 13-5. Interrupt Processing MC68HC908GR16 Data Sheet, Rev. 5.
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Interrupts Table 13-1.
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Resets and Interrupts 13.3.2.1 Software Interrupt (SWI) Instruction The software interrupt (SWI) instruction causes a non-maskable interrupt. NOTE A software interrupt pushes PC onto the stack. An SWI does not push PC – 1, as a hardware interrupt does. 13.3.2.2 Break Interrupt The break module causes the CPU to execute an SWI instruction at a software-programmable break point. 13.3.2.3 IRQ Pin A 0 on the IRQ1 pin latches an external interrupt request. 13.3.2.
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Interrupts • • • SPI transmitter empty (SPTE) — The SPTE bit is set every time a byte transfers from the transmit data register to the shift register. The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU interrupt requests. SPTE is in the SPI status and control register and SPTIE is in the SPI control register. Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the SS pin goes high during a transmission with the mode fault enable bit (MODFEN) set.
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Resets and Interrupts 13.3.2.9 KBD0–KBD7 Pins A 0 on a keyboard interrupt pin latches an external interrupt request. 13.3.2.10 Analog-to-Digital Converter (ADC) When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. The COCO bit is not used as a conversion complete flag when interrupts are enabled. 13.3.2.11 Timebase Module (TBM) The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2–TBR0.
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Interrupts 13.3.3.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 13-6. Interrupt Status Register 1 (INT1) IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Table 13-2. 1 = Interrupt request present 0 = No interrupt request present Bit 1 and Bit 0 — Always read 0 13.3.3.
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Resets and Interrupts MC68HC908GR16 Data Sheet, Rev. 5.
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Chapter 14 Enhanced Serial Communications Interface (ESCI) Module 14.1 Introduction The enhanced serial communications interface (ESCI) module allows asynchronous communications with peripheral devices and other microcontroller units (MCU). 14.
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Enhanced Serial Communications Interface (ESCI) Module INTERNAL BUS USER FLASH VECTOR SPACE — 36 BYTES DDRA DDRB DDRC 2-CHANNEL TIMER INTERFACE MODULE 1 FLASH PROGRAMMING ROUTINES ROM — 406 BYTES 2-CHANNEL TIMER INTERFACE MODULE 2 CLOCK GENERATOR MODULE VSSAD/VREFL PHASE LOCKED LOOP DDRD SYSTEM INTEGRATION MODULE PTE5–PTE2 PTE1/RxD PTE0/TxD SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE DDRE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE MEMORY MAP MODULE POWER
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Functional Description 14.4 Functional Description Figure 14-2 shows the structure of the ESCI module. The ESCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the ESCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the ESCI, writes the data to be transmitted, and processes received data.
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Enhanced Serial Communications Interface (ESCI) Module The baud rate clock source for the ESCI can be selected via the configuration bit, ESCIBDSRC, of the CONFIG2 register ($001E). For reference, a summary of the ESCI module input/output registers is provided in Figure 14-3. Addr. $0009 $000A Register Name ESCI Prescaler Register Read: (SCPSC) Write: See page 170. Reset: ESCI Arbiter Control Read: Register (SCIACTL) Write: See page 174.
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Functional Description PARITY OR DATA BIT 8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 STOP BIT PARITY OR DATA BIT 9-BIT DATA FORMAT (BIT M IN SCC1 SET) START BIT NEXT START BIT BIT 6 BIT 7 BIT 8 NEXT START BIT STOP BIT Figure 14-4. SCI Data Formats 14.4.2 Transmitter Figure 14-5 shows the structure of the SCI transmitter and the registers are summarized in Figure 14-3.
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Enhanced Serial Communications Interface (ESCI) Module 14.4.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). 14.4.2.2 Character Transmission During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin.
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Functional Description • • • Clears the R8 bit in SCC3 Sets the break flag bit (BKF) in SCS2 May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits 14.4.2.4 Idle Characters For TXINV = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission.
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Enhanced Serial Communications Interface (ESCI) Module 14.4.3 Receiver Figure 14-6 shows the structure of the ESCI receiver. The receiver I/O registers are summarized in Figure 14-3.
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Functional Description 14.4.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 14.4.3.2 Character Reception During an ESCI reception, the receive shift register shifts characters in from the RxD pin.
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Enhanced Serial Communications Interface (ESCI) Module Table 14-2. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10.
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Functional Description 14.4.3.4 Framing Errors If the data recovery logic does not detect a 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. 14.4.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate.
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Enhanced Serial Communications Interface (ESCI) Module Fast Data Tolerance Figure 14-9 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. STOP IDLE OR NEXT CHARACTER RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK DATA SAMPLES Figure 14-9.
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Low-Power Modes 2. Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the ESCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit.
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Enhanced Serial Communications Interface (ESCI) Module 14.5.2 Stop Mode The ESCI module is inactive in stop mode. The STOP instruction does not affect ESCI register states. ESCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an ESCI transmission or reception results in invalid data. 14.
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I/O Registers • • • ESCI prescaler register, SCPSC ESCI arbiter control register, SCIACTL ESCI arbiter data register, SCIADAT 14.8.
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Enhanced Serial Communications Interface (ESCI) Module Table 14-5.
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I/O Registers • • • • Enables the transmitter Enables the receiver Enables ESCI wakeup Transmits ESCI break characters Address: $0014 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 14-11. ESCI Control Register 2 (SCC2) SCTIE — ESCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate ESCI transmitter CPU interrupt requests.
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Enhanced Serial Communications Interface (ESCI) Module RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE Writing to the RE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1.
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I/O Registers When the ESCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the ESCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset clears the T8 bit.
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Enhanced Serial Communications Interface (ESCI) Module SCTE — ESCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an ESCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an ESCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
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I/O Registers In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register.
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Enhanced Serial Communications Interface (ESCI) Module 14.8.5 ESCI Status Register 2 ESCI status register 2 (SCS2) contains flags to signal these conditions: • Break character detected • Incoming data Address: Read: $0017 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 BKF RPF 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 14-15. ESCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the ESCI detects a break character on the RxD pin.
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I/O Registers 14.8.7 ESCI Baud Rate Register The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for both the receiver and the transmitter. NOTE There are two prescalers available to adjust the baud rate. One in the ESCI baud rate register and one in the ESCI prescaler register. Address: Read: Write: Reset: $0019 Bit 7 6 5 4 3 2 1 Bit 0 LINT LINR SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 0 0 R = Reserved = Unimplemented Figure 14-17.
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Enhanced Serial Communications Interface (ESCI) Module SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits These read/write bits select the baud rate register prescaler divisor as shown in Table 14-7. Reset clears SCP1 and SCP0. Table 14-7. ESCI Baud Rate Prescaling SCP[1:0] Baud Rate Register Prescaler Divisor (BPD) 0 0 1 0 1 3 1 0 4 1 1 13 SCR2–SCR0 — ESCI Baud Rate Select Bits These read/write bits select the ESCI baud rate divisor as shown in Table 14-8. Reset clears SCR2–SCR0. Table 14-8.
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I/O Registers PDS2–PDS0 — Prescaler Divisor Select Bits These read/write bits select the prescaler divisor as shown in Table 14-9. Reset clears PDS2–PDS0. NOTE The setting of ‘000’ will bypass not only this prescaler but also the prescaler divisor fine adjust (PDFA). It is not recommended to bypass the prescaler while ENSCI is set, because the switching is not glitch free. Table 14-9.
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Enhanced Serial Communications Interface (ESCI) Module Table 14-10. ESCI Prescaler Divisor Fine Adjust PSSB[4:3:2:1:0] Prescaler Divisor Fine Adjust (PDFA) 0 0 0 0 0 0/32 = 0 0 0 0 0 1 1/32 = 0.03125 0 0 0 1 0 2/32 = 0.0625 0 0 0 1 1 3/32 = 0.09375 0 0 1 0 0 4/32 = 0.125 0 0 1 0 1 5/32 = 0.15625 0 0 1 1 0 6/32 = 0.1875 0 0 1 1 1 7/32 = 0.21875 0 1 0 0 0 8/32 = 0.25 0 1 0 0 1 9/32 = 0.28125 0 1 0 1 0 10/32 = 0.3125 0 1 0 1 1 11/32 = 0.34375 0 1 1 0 0 12/32 = 0.
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I/O Registers Table 14-11. ESCI Baud Rate Selection Examples PS[2:1:0] PSSB[4:3:2:1:0] SCP[1:0] Prescaler Divisor (BPD) SCR[2:1:0] Baud Rate Divisor (BD) 0 0 0 X X X X X 0 0 1 0 0 0 1 76,800 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 9600 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 9562.65 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 9525.58 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 8563.
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Enhanced Serial Communications Interface (ESCI) Module 14.9 ESCI Arbiter The ESCI module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time detection. The arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. The CPU can control operation mode via the ESCI arbiter control register (SCIACTL). 14.9.
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ESCI Arbiter ARUN— Arbiter Counter Running Flag This read-only bit indicates the arbiter counter is running. Reset clears ARUN. 1 = Arbiter counter running 0 = Arbiter counter stopped AROVFL— Arbiter Counter Overflow Bit This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to SCIACTL. Writing 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears AROVFL.
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Enhanced Serial Communications Interface (ESCI) Module MEASURED TIME CPU READS RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 COUNTER STARTS, ARUN = 1 CPU WRITES SCIACTL WITH $20 RXD Figure 14-21. Bit Time Measurement with ACLK = 0 MEASURED TIME CPU READS RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 CPU WRITES SCIACTL WITH $30 COUNTER STARTS, ARUN = 1 RXD Figure 14-22.
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Chapter 15 System Integration Module (SIM) 15.1 Introduction This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 15-2. Table 15-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing.
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System Integration Module (SIM) INTERNAL BUS CLOCK GENERATOR MODULE IRQ(3) VDDAD/VREFH VSSAD/VREFL DDRA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE DDRD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE 32–100 kHz OSCILLATOR SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE MEMORY MAP MODULE
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SIM Bus Clock Control and Generation MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM) SIM COUNTER CGMXCLK (FROM CGM) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL VDD CLOCK GENERATORS INTERNAL PULLUP DEVICE RESET PIN LOGIC INTERNAL CLOCKS FORCED MONITOR MODE ENTRY LVI (FROM LVI MODULE) POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) R
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System Integration Module (SIM) Addr. Register Name $FE00 Break Status Register Read: (BSR) Write: See page 192. Reset: Bit 7 6 5 4 3 2 1 Bit 0 R R R R R R 0 0 0 0 0 0 0 0 SBSW Note(1) R 1. Writing a a 0 clears SBSW. $FE01 $FE03 SIM Reset Status Register Read: (SRSR) Write: See page 193. POR: Break Flag Control Register Read: (BFCR) Write: See page 194.
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Reset and System Initialization 15.2.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt or reset, the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. See 15.6.2 Stop Mode. In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
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System Integration Module (SIM) 15.3.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. See Figure 15-6. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. See Figure 15-7.
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Reset and System Initialization OSC1 PORRST 4096 CYCLES 32 CYCLES CGMXCLK CGMOUT RST $FFFE IAB $FFFF Figure 15-8. POR Recovery 15.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources.
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System Integration Module (SIM) Thirty-two CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 15.3.2.6 Monitor Mode Entry Module Reset (MODRST) The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is entered in the condition where the reset vectors are erased ($FF) (see 19.3.1.1 Normal Monitor Mode).
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Exception Control 15.5.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 15-9 shows interrupt entry timing. Figure 15-10 shows interrupt recovery timing.
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System Integration Module (SIM) FROM RESET BREAK I BIT SET? INTERRUPT? YES NO YES I BIT SET? NO IRQ INTERRUPT? YES NO AS MANY INTERRUPTS AS EXIST ON CHIP STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 15-11. Interrupt Processing 15.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction.
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Exception Control If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 15-12 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
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System Integration Module (SIM) Table 15-3.
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Exception Control Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: I14 I13 I12 I11 I10 I9 I8 I7 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 15-14. Interrupt Status Register 2 (INT2) I14–I7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown in Table 15-3.
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System Integration Module (SIM) Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. 15.
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Low-Power Modes 32 CYCLES IAB IDB 32 CYCLES $6E0B $A6 RSTVCT H $A6 RSTVCTL $A6 RST CGMXCLK Figure 15-18. Wait Recovery from Internal Reset 15.6.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset also causes an exit from stop mode.
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System Integration Module (SIM) STOP RECOVERY PERIOD CGMXCLK INT/BREAK IAB STOP + 2 STOP +1 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 15-20. Stop Mode Recovery from Interrupt 15.7 SIM Registers The SIM has three memory-mapped registers. Table 15-4 shows the mapping of these registers. Table 15-4. SIM Registers Address Register Access Mode $FE00 BSR User $FE01 SRSR User $FE03 BFCR User 15.7.
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SIM Registers 15.7.2 SIM Reset Status Register This register contains seven flags that show the source of the last reset provided all previous reset status bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register. Address: Read: $FE01 Bit 7 6 5 4 3 2 1 Bit 0 POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 15-22.
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System Integration Module (SIM) 15.7.3 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 15-23.
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Chapter 16 Serial Peripheral Interface (SPI) Module 16.1 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 16.
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Serial Peripheral Interface (SPI) Module INTERNAL BUS USER FLASH VECTOR SPACE — 36 BYTES DDRA DDRB DDRC 2-CHANNEL TIMER INTERFACE MODULE 1 FLASH PROGRAMMING ROUTINES ROM — 406 BYTES 2-CHANNEL TIMER INTERFACE MODULE 2 CLOCK GENERATOR MODULE VSSAD/VREFL PHASE LOCKED LOOP DDRD SYSTEM INTEGRATION MODULE PTE5–PTE2 PTE1/RxD PTE0/TxD SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE DDRE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE MEMORY MAP MODULE POWER-ON RESET MODU
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Functional Description 16.4 Functional Description Figure 16-2 summarizes the SPI I/O registers and Figure 16-3 shows the structure of the SPI module. The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt driven. If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. See 12.4.
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Serial Peripheral Interface (SPI) Module INTERNAL BUS TRANSMIT DATA REGISTER CGMOUT ÷ 2 FROM SIM SHIFT REGISTER 7 6 5 4 3 2 1 MISO 0 ÷2 CLOCK DIVIDER MOSI ÷8 RECEIVE DATA REGISTER ÷ 32 PIN CONTROL LOGIC ÷ 128 SPMSTR CLOCK SELECT SPE SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR RESERVED TRANSMITTER CPU INTERRUPT REQUEST RESERVED CPHA MODFEN CPOL SPWOM ERRIE SPI CONTROL SPTIE SPRIE RECEIVER/ERROR CPU INTERRUPT REQUEST SPE SPRF SPTE OVRF MODF Figure 16-3.
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Transmission Formats As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register.
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Serial Peripheral Interface (SPI) Module The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
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Transmission Formats MISO/MOSI BYTE 1 BYTE 2 BYTE 3 MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 Figure 16-6. CPHA/SS Timing 16.5.3 Transmission Format When CPHA = 1 Figure 16-7 shows an SPI transmission in which CPHA is 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1.
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Serial Peripheral Interface (SPI) Module signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. (See Figure 16-8.) The internal SPI clock in the master is a free-running derivative of the internal MCU clock.
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Queuing Transmission Data 16.6 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high.
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Serial Peripheral Interface (SPI) Module 16.7 Error Conditions The following flags signal SPI error conditions: • Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register.
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Error Conditions BYTE 1 BYTE 2 BYTE 3 BYTE 4 1 4 6 8 SPRF OVRF READ SPSCR 2 5 READ SPDR 3 7 1 BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT. 3 4 5 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 6 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 7 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. 8 BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
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Serial Peripheral Interface (SPI) Module 16.7.2 Mode Fault Error Setting the SPMSTR bit selects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR.
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Interrupts In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by clearing the SPE bit of the slave. NOTE A 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission.
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Serial Peripheral Interface (SPI) Module NOT AVAILABLE SPTE SPTIE SPE SPI TRANSMITTER CPU INTERRUPT REQUEST NOT AVAILABLE SPRIE SPRF SPI RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE MODF OVRF Figure 16-12. SPI Interrupt Request Generation 16.9 Resetting the SPI Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: • The SPTE flag is set. • Any transmission currently in progress is aborted.
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SPI During Break Interrupts 16.10.1 Wait Mode The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction.
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Serial Peripheral Interface (SPI) Module 16.12.1 MISO (Master In/Slave Out) MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave.
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I/O Registers NOTE A 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-impedance state. The slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See 16.7.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set.
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Serial Peripheral Interface (SPI) Module Address: $0010 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE 0 0 1 0 1 0 0 0 R = Reserved = Unimplemented Figure 16-14. SPI Control Register (SPCR) SPRIE — SPI Receiver Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
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I/O Registers 16.13.
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Serial Peripheral Interface (SPI) Module MODFEN bit set. Clear the MODF bit by reading the SPI status and control register (SPSCR) with MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE — SPI Transmitter Empty Bit This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register.
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I/O Registers 16.13.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. See Figure 16-3.
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Serial Peripheral Interface (SPI) Module MC68HC908GR16 Data Sheet, Rev. 5.
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Chapter 17 Timebase Module (TBM) 17.1 Introduction This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the external clock source. This TBM version uses 15 divider stages, eight of which are user selectable. A configuration option bit to select an additional 128 divide of the external clock source can be selected. See Chapter 5 Configuration Register (CONFIG) 17.
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Timebase Module (TBM) TMBCLKSEL FROM CONFIG2 CGMXCLK FROM CGM MODULE TBMCLK 0 1 DIVIDE BY 128 PRESCALER TBON ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 TACK ÷2 TBR0 ÷2 TBR1 ÷2 TBR2 TBMINT TBIF 000 TBIE R 001 010 100 SEL 011 101 110 111 Figure 17-1. Timebase Block Diagram 17.
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Low-Power Modes Table 17-1. Timebase Divider Selection Divider Tap TBR2 TBR1 TBR0 TMBCLKSEL 0 1 0 0 0 32,768 4,194,304 0 0 1 8192 1,048,576 0 1 0 2048 262144 0 1 1 128 16,384 1 0 0 64 8192 1 0 1 32 4096 1 1 0 16 2048 1 1 1 8 1024 As an example, a clock source of 4.9152 MHz, with the TMBCLKSEL set for divide-by-128 and the TBR2–TBR0 set to {011}, the divider tap is1 and the interrupt rate calculates to: 1/(4.
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Timebase Module (TBM) 17.7 Timebase Control Register The timebase has one register, the timebase control register (TBCR), which is used to enable the timebase interrupts and set the rate. Address: $001C Bit 7 Read: TBIF Write: Reset: 0 6 5 4 TBR2 TBR1 TBR0 0 0 0 = Unimplemented 3 2 1 Bit 0 TBIE TBON R 0 0 0 0 R = Reserved 0 TACK Figure 17-2. Timebase Control Register (TBCR) TBIF — Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over.
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Chapter 18 Timer Interface Module (TIM) 18.1 Introduction This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 18-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
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Timer Interface Module (TIM) INTERNAL BUS CLOCK GENERATOR MODULE IRQ(3) VDDAD/VREFH VSSAD/VREFL DDRA PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5–PTE2 PTE1/RxD PTE0/TxD PHASE LOCKED LOOP SYSTEM INTEGRATION MODULE DDRD ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE 32–100 kHz OSCILLATOR SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE MEMORY MAP MODULE PO
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Features 18.2 Features Features of the TIM include: • Two input capture/output compare channels: – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action • Buffered and unbuffered pulse-width-modulation (PWM) signal generation • Programmable TIM clock input with 7-frequency internal bus clock prescaler selection • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIM counter stop and reset bits 18.
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Timer Interface Module (TIM) Addr. $0020 $0021 $0022 Register Name Bit 7 Timer 1 Status and Control Read: Register (T1SC) Write: See page 231. Reset: TOF $0025 $0026 $0027 $002A $002B 4 3 0 0 2 1 Bit 0 PS2 PS1 PS0 TSTOP 0 0 1 0 0 0 0 0 Timer 1 Counter Read: Register High (T1CNTH) Write: See page 232. Reset: Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Timer 1 Counter Read: Register Low (T1CNTL) Write: See page 232.
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Functional Description Addr. $002C $002D Register Name Bit 7 6 5 4 3 2 1 Bit 0 Timer 2 Counter Read: Register High (T2CNTH) Write: See page 232. Reset: Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Timer 2 Counter Read: Register Low (T2CNTL) Write: See page 232.
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Timer Interface Module (TIM) into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. 18.4.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin.
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Functional Description 18.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal.
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Timer Interface Module (TIM) • When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare.
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Interrupts c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Table 18-3. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise.
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Timer Interface Module (TIM) 18.6.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. 18.7 TIM During Break Interrupts A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state.
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I/O Registers 18.9.1 TIM Status and Control Register The TIM status and control register (TSC): • Enables TIM overflow interrupts • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter clock Address: T1SC, $0020 and T2SC, $002B Bit 7 Read: TOF Write: 0 Reset: 0 6 5 TOIE TSTOP 0 1 4 3 0 0 TRST 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 0 = Unimplemented Figure 18-5.
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Timer Interface Module (TIM) NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 18-2 shows. Reset clears the PS[2:0] bits. Table 18-2.
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I/O Registers 18.9.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
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Timer Interface Module (TIM) Address: T1SC1, $0028 and T2SC1, $0033 Bit 7 Read: CH1F Write: 0 Reset: 0 6 5 CH1IE 0 0 0 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 Figure 18-11. TIM Channel 1 Status and Control Register (TSC1) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin.
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I/O Registers ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTDx/TCHx is available as a general-purpose I/O pin. Table 18-3 shows how ELSxB and ELSxA work.
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Timer Interface Module (TIM) OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW PERIOD TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE CHxMAX Figure 18-12. CHxMAX Latency 18.9.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown.
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Chapter 19 Development Support 19.1 Introduction This section describes the break module, the monitor read-only memory (MON), and the monitor mode entry methods. 19.2 Break Module (BRK) This subsection describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
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Development Support ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] BKPT (TO SIM) CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] Figure 19-1. Break Module Block Diagram Addr. Register Name $FE00 Break Status Register Read: (BSR) Write: See page 241. Reset: $FE02 Break Auxiliary Register Read: (BRKAR) Write: See page 240. Reset: $FE03 Break Flag Control Read: Register (BFCR) Write: See page 241.
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Break Module (BRK) 19.2.1.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 19.2.1.
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Development Support 19.2.2.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: $FE09 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 19-4.
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Break Module (BRK) 19.2.2.4 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Address: $FE00 Bit 7 Read: Write: R 6 5 R R 4 R 3 R 2 R 1 SBSW Note(1) Reset: Bit 0 R 0 R = Reserved 1. Writing a 0 clears SBSW. Figure 19-7. Break Status Register (BSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine.
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Development Support 19.3 Monitor ROM (MON) This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
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Monitor ROM (MON) • If $FFFE and $FFFF contain $FF (erased state): – The external clock is 32.768 kHz – IRQ = VSS The last two conditions are the forced monitor mode.
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Development Support MC68HC908GR16 N.C. RST VDD 47 pF 1 1 μF + 3 4 1 μF + VDD VCC C1+ + + 3 PTB4 7 10 8 9 1 kΩ PTB0 IRQ VDD V– 6 DB9 10 k C3 VTST + VDD OSC1 9.8304 MHz V+ 2 C2+ 5 C2– 2 C5 0.1 μF 10 MΩ 27 pF 16 GND 15 C1– VDDA OSC2 MAX232 C4 10 k 10 k PTB1 10 k PTA1 10 kΩ 74HC125 5 6 74HC125 3 2 VDD PTA0 VSSA VSS 4 1 5 Figure 19-10. Normal Monitor Mode Circuit MC68HC908GR16 N.C.
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Monitor ROM (MON) MC68HC908GR16 N.C. 33 pF 1 μF + 3 4 1 μF + C1+ VDD VCC + GND 15 C2+ V+ 2 3 + 7 10 8 9 0.1 μF C3 IRQ VDD + VDDA OSC1 32.768 kHz V– 6 DB9 2 C5 VDD 10 MΩ 15 pF 16 C1– 5 C2– 10 k OSC2 MAX232 1 RST VDD 4.7 k PTB4 N.C. PTB0 N.C. PTB1 N.C. 10 k C4 74HC125 5 6 74HC125 3 2 PTA1 10 kΩ PTA0 4 VSSA VSS 1 5 Figure 19-12.
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Mode — Normal Monitor IRQ X GND VDD VTST or VTST VTST MC68HC908GR16 Data Sheet, Rev. 5.0 Forced Monitor User RST VDD or VTST Reset Vector Divider PLL COP X X Communication Speed Comments External Bus Baud Clock Frequency Rate X X X Reset condition PTA1 PTB0 PTB1 PTB4 X X X X X X X 1 0 1 0 0 OFF Disabled 4.9152 MHz 2.4576 MHz 9600 X 1 0 1 0 1 OFF Disabled 9.8304 MHz 2.4576 MHz 9600 1 0 X X X OFF Disabled 16 MHz 4 MHz 9600 1 0 X X X ON 32.768 kHz 2.
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Monitor ROM (MON) This condition states that as long as VTST is maintained on the IRQ pin after entering monitor mode, or if VTST is applied to RST after the initial reset to get into monitor mode (when VTST was applied to IRQ), then the COP will be disabled. In the latter situation, after VTST is applied to the RST pin, VTST can be removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode. 19.3.1.
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Development Support 19.3.1.5 Break Signal A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal. MISSING STOP BIT 0 1 2 3 4 5 6 2-STOP BIT DELAY BEFORE ZERO ECHO 0 7 1 2 3 4 5 6 7 Figure 19-14. Break Transaction 19.3.1.
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Monitor ROM (MON) FROM HOST 3 ADDRESS HIGH WRITE WRITE 3 1 ADDRESS HIGH 1 ADDRESS LOW 3 ADDRESS LOW 1 DATA 3 DATA 1 2, 3 ECHO Notes: 1 = Echo delay, 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte. Figure 19-16. Write Transaction A brief description of each monitor mode command is given in Table 19-3 through Table 19-8. Table 19-3.
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Development Support Table 19-5. IREAD (Indexed Read) Command Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence FROM HOST IREAD IREAD DATA DATA ECHO RETURN Table 19-6.
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Monitor ROM (MON) Table 19-8. RUN (Run User Program) Command Description Executes PULH and RTI instructions Operand None Data Returned None Opcode $28 Command Sequence FROM HOST RUN RUN ECHO The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program.
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Development Support Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command.
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Chapter 20 Electrical Specifications 20.1 Introduction This section contains electrical and timing specifications. 20.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 20.5 5.0-Vdc Electrical Characteristics and 20.6 3.3-Vdc Electrical Characteristics for guaranteed operating conditions.
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Electrical Specifications 20.3 Functional Operating Range Characteristic Symbol Value Unit TA –40 to +125 °C VDD 5.0 ±10% 3.3 ±10% V Symbol Value Unit Thermal resistance 32-pin LQFP 48-pin LQFP θJA 95 95 °C/W I/O pin power dissipation PI/O User determined W Power dissipation(1) PD PD = (IDD × VDD) + PI/O = K/(TJ + 273 °C) W Constant(2) K Average junction temperature Maximum junction temperature Operating temperature range Operating voltage range 20.
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5.0-Vdc Electrical Characteristics 20.5 5.0-Vdc Electrical Characteristics Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.8 VDD – 1.5 VDD – 1.5 — — — — — — — V V V — 50 mA IOH2 — — 50 mA IOHT — — 100 mA VOL VOL VOL IOL1 — — — — — — 0.4 1.5 1.5 V V V — — 50 mA IOL2 — — 50 mA IOLT — — 100 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.
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Electrical Specifications Symbol Min Typ(2) Max Unit VTST VDD + 2.5 — VDD + 4.0 V Low-voltage inhibit, trip falling voltage VTRIPF 3.9 4.25 4.50 V Low-voltage inhibit, trip rising voltage VTRIPR 4.2 4.35 4.60 V Low-voltage inhibit reset/recover hysteresis (VTRIPF + VHYS = VTRIPR) VHYS — 60 — mV POR rearm voltage(8) VPOR 0 — 100 mV POR reset voltage(9) VPORRST 0 700 800 mV RPOR 0.
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3.3-Vdc Electrical Characteristics 20.6 3.3-Vdc Electrical Characteristics Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.3 VDD – 1.0 VDD – 1.0 — — — — — — — V V V — 30 mA IOH2 — — 30 mA IOHT — — 60 mA VOL VOL VOL IOL1 — — — — — — 0.3 1.0 0.8 V V V — — 30 mA IOL2 — — 30 mA IOLT — — 60 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.
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Electrical Specifications Symbol Min Typ(2) Max Unit VTST VDD + 2.5 — VDD + 4.0 V Low-voltage inhibit, trip falling voltage VTRIPF 2.35 2.6 2.7 V Low-voltage inhibit, trip rising voltage VTRIPR 2.4 2.66 2.8 V Low-voltage inhibit reset/recover hysteresis (VTRIPF + VHYS = VTRIPR) VHYS — 100 — mV POR rearm voltage(8) VPOR 0 — 100 mV POR reset voltage(9) VPORRST 0 700 800 mV RPOR 0.
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5.0-Volt Control Timing 20.7 5.0-Volt Control Timing Characteristic(1) Symbol Min Max Unit fOSC 32 dc 100 32.8 kHz MHz fOP (fBus) — 8.2 MHz tCYC 122 — ns tIRL 50 — ns IRQ interrupt pulse width low(4) (edge-triggered) tILIH 50 — ns IRQ interrupt pulse period tILIL Note 5 — tCYC Frequency of operation Crystal option External clock option(2) Internal operating frequency Internal clock period (1/fOP) RESET input pulse width low 1. 2. 3. 4.
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Electrical Specifications 20.9 Clock Generation Module Characteristics 20.9.1 CGM Component Specifications Characteristic Symbol Min Typ Max Unit fXCLK 30 32.768 100 kHz Crystal load capacitance(1) CL — 12.5 — pF Crystal fixed capacitance(2) C1 — 15 — pF Crystal tuning capacitance C2 — 15 — pF Feedback bias resistor RB 1 10 22 MΩ Series resistor(3) RS 100 330 470 kΩ External clock 1. Crystal manufacturer value 2. Capacitor on OSC1 pin.
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5.0-Volt ADC Characteristics 20.10 5.0-Volt ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 4.5 5.5 V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VDDAD Resolution BAD 10 10 Bits Absolute accuracy AAD –4 +4 Counts Includes quantization ADC internal clock fADIC 500 k 1.
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Electrical Specifications 20.11 3.3-Volt ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 3.0 3.6 V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VDDAD Resolution BAD 10 10 Bits Absolute accuracy AAD –6 +6 Counts Includes quantization ADC internal clock fADIC 500 k 1.
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5.0-Volt SPI Characteristics 20.13 5.0-Volt SPI Characteristics Diagram Number(1) 1. 2. 3. 4. 5.
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Electrical Specifications 20.14 3.3-Volt SPI Characteristics Diagram Number(1) 1. 2. 3. 4. 5.
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3.3-Volt SPI Characteristics SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT MSB IN BITS 6–1 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
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Electrical Specifications SS INPUT 3 1 SPSCK INPUT CPOL = 0 5 4 2 SPSCK INPUT CPOL = 1 5 4 9 8 MISO INPUT SLAVE MSB OUT 6 MOSI OUTPUT BITS 6–1 7 NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT CPOL = 0 5 4 2 3 SPSCK INPUT CPOL = 1 8 MISO OUTPUT MOSI INPUT 5 4 10 NOTE 9 SLAVE MSB OUT 6 7 BITS 6–1 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defin
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Memory Characteristics 20.15 Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz FLASH read bus clock frequency fRead(1) 0 — 8M Hz FLASH page erase time Limited endurance (<1 K cycles) Maximum endurance (>1 K cycles) tErase(2) 0.9 3.6 1 4 1.1 5.
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Electrical Specifications MC68HC908GR16 Data Sheet, Rev. 5.
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Chapter 21 Ordering Information and Mechanical Specifications 21.1 Introduction This section provides ordering information for the MC68HC908GR16 along with the dimensions for: • 48-pin low-profile quad flat pack (LQFP) • 32-pin low-profile quad flat pack (LQFP) The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Semiconductor Sales Office. 21.2 MC Order Numbers Table 21-1.
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.