Datasheet

Functional Description
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 101
Figure 8-2. IRQ Module Block Diagram
When an interrupt pin is both falling-edge and low-level triggered (MODE = 1), the interrupt remains set
until both of these events occur:
• Vector fetch or software clear
• Return of the interrupt pin to 1
The vector fetch or software clear may occur before or after the interrupt pin returns to 1. As long as the
pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
Addr.Register Name Bit 7654321Bit 0
$001D
IRQ Status and Control
Register (INTSCR)
See page 103.
Read:0000IRQF0
IMASK MODE
Write:
ACK
Reset:00000000
= Unimplemented
Figure 8-3. IRQ I/O Register Summary
IMASK
DQ
CK
CLR
IRQ
HIGH
INTERRUPT
TO MODE
SELECT
LOGIC
REQUEST
V
DD
MODE
VOLTAGE
DETECT
IRQF
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
INTERNAL ADDRESS BUS
RESET
V
DD
INTERNAL
PULLUP
DEVICE
ACK
IRQ
SYNCHRONIZER