Datasheet

IRQ Status and Control Register
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 103
8.6 IRQ Status and Control Register
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ
interrupt pin.
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ
interrupt pending
0 = IRQ
interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ
pin. Reset clears MODE.
1 = IRQ
interrupt requests on falling edges and low levels
0 = IRQ
interrupt requests on falling edges only
Address: $001D
Bit 7654321Bit 0
Read:
IRQF 0
IMASK MODE
Write:
ACK
Reset:00000000
= Unimplemented
Figure 8-4. IRQ Status and Control Register (INTSCR)