Datasheet

LVI Status Register
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 119
11.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
DD
fall below V
TRIPF
), the LVI will maintain a reset condition until
V
DD
rises above the rising trip point voltage, V
TRIPR
. This prevents a condition in which the MCU is
continually entering and exiting reset if V
DD
is approximately equal to V
TRIPF
. V
TRIPR
is greater than
V
TRIPF
by the hysteresis voltage, V
HYS
.
11.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V
protection.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (V
TRIPF
[5 V] or V
TRIPF
[3 V]) may be lower than this. See
Chapter 20 Electrical Specifications for the actual trip point voltages.
11.4 LVI Status Register
The LVI status register (LVISR) indicates if the V
DD
voltage was detected below the V
TRIPF
level.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
DD
voltage falls below the V
TRIPF
trip voltage (see Table
11-1). Reset clears the LVIOUT bit.
11.5 LVI Interrupts
The LVI module does not generate interrupt requests.
11.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
Address: $FE0C
Bit 7654321Bit 0
Read:LVIOUT0000000
Write:
Reset:00000000
= Unimplemented
Figure 11-3. LVI Status Register (LVISR)
Table 11-1. LVIOUT Bit Indication
V
DD
LVIOUT
V
DD
> V
TRIPR
0
V
DD
< V
TRIPF
1
V
TRIPF
< V
DD
< V
TRIPR
Previous value