Datasheet

Port C
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 129
Figure 12-11. Port C I/O Circuit
When bit DDRCx is a 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a 0,
reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port C pins.
12.4.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each
of the port C pins. Each bit is individually configurable and requires that the data direction register, DDRC,
bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s
DDRC is configured for output mode.
Table 12-4. Port C Pin Functions
PTCPUE
Bit
DDRC
Bit
PTC
Bit
I/O Pin
Mode
Accesses to DDRC Accesses to PTC
Read/Write Read Write
10
X
(1)
1. X = Don’t care
Input, V
DD
(2)
2. I/O pin pulled up to V
DD
by internal pullup device.
DDRC6–DDRC0 Pin
PTC6–PTC0
(3)
3. Writing affects data register, but does not affect input.
00X
Input, Hi-Z
(4)
4. Hi-Z = High impedance
DDRC6–DDRC0 Pin
PTC6–PTC0
(3)
X 1 X Output DDRC6–DDRC0 PTC6–PTC0 PTC6–PTC0
Address: $000E
Bit 7654321Bit 0
Read: 0
PTCPUE6 PTCPUE5 PTCPUE4 PTCPUE3 PTCPUE2 PTCPUE1 PTCPUE0
Write:
Reset:00000000
= Unimplemented
Figure 12-12. Port C Input Pullup Enable Register (PTCPUE)
READ DDRC ($0006)
WRITE DDRC ($0006)
RESET
WRITE PTC ($0002)
READ PTC ($0002)
PTCx
DDRCx
PTCx
INTERNAL DATA BUS
V
DD
INTERNAL
PTCPUEx
PULLUP
DEVICE