Datasheet

Resets and Interrupts
MC68HC908GR16 Data Sheet, Rev. 5.0
136 Freescale Semiconductor
A power-on reset:
• Holds the clocks to the central processor unit (CPU) and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles
• Drives the RST
pin low during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
• Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
• Sets the POR and LVI bits in the SIM reset status register and clears all other bits in the register
Figure 13-1. Power-On Reset Recovery
13.2.3.2 Computer Operating Properly (COP) Reset
A computer operating properly (COP) reset is an internal reset caused by an overflow of the COP counter.
A COP reset sets the COP bit in the SIM reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
13.2.3.3 Low-Voltage Inhibit (LVI) Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the
LVI
TRIPF
voltage.
An LVI reset:
• Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles after the power supply voltage rises to the LVI
TRIPR
voltage
• Drives the RST
pin low for as long as V
DD
is below the LVI
TRIPR
voltage and during the oscillator
stabilization delay
• Releases the RST
pin 32 CGMXCLK cycles after the oscillator stabilization delay
• Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
• Sets the LVI bit in the SIM reset status register
PORRST
(1)
OSC1
CGMXCLK
CGMOUT
RST
PIN
4096
CYCLES
32
CYCLES
1. PORRST is an internally generated power-on reset pulse.