Datasheet

Resets and Interrupts
MC68HC908GR16 Data Sheet, Rev. 5.0
138 Freescale Semiconductor
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR since any reset
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by forced monitor mode entry.
0 = POR or read of SRSR since any reset
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR since any reset
13.3 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. An
interrupt does not stop the operation of the instruction being executed, but begins when the current
instruction completes its operation.
13.3.1 Effects
An interrupt:
• Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the
CPU registers from the stack so that normal processing can resume.
• Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other
interrupt can take precedence, regardless of its priority.
• Loads the program counter with a user-defined vector address
Figure 13-3. Interrupt Stacking Order
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE)
(1)
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
•
1
2
3
4
5
5
4
3
2
1
STACKING
ORDER
1. High byte of index register is not stacked.
$00FF DEFAULT ADDRESS ON RESET
UNSTACKING
ORDER