Datasheet

Resets and Interrupts
MC68HC908GR16 Data Sheet, Rev. 5.0
144 Freescale Semiconductor
13.3.2.9 KBD0–KBD7 Pins
A 0 on a keyboard interrupt pin latches an external interrupt request.
13.3.2.10 Analog-to-Digital Converter (ADC)
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
13.3.2.11 Timebase Module (TBM)
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2–TBR0. When
the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
Interrupts must be acknowledged by writing a 1 to the TACK bit.
13.3.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 13-2 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 13-2. Interrupt Source Flags
Interrupt
Source
Interrupt Status
Register Flag
Reset —
SWI instruction —
IRQ
pin IF1
CGM change of lock IF2
TIM1 channel 0 IF3
TIM1 channel 1 IF4
TIM1 overflow IF5
TIM2 channel 0 IF6
TIM2 channel 1 IF7
TIM2 overflow IF8
SPI receive IF9
SPI transmit IF10
SCI error IF11
SCI receive IF12
SCI transmit IF13
Keyboard IF14
ADC conversion complete IF15
Timebase IF16