Datasheet

Functional Description
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 151
Figure 14-4. SCI Data Formats
14.4.2 Transmitter
Figure 14-5 shows the structure of the SCI transmitter and the registers are summarized in Figure 14-3.
The baud rate clock source for the ESCI can be selected via the configuration bit, ESCIBDSRC.
Figure 14-5. ESCI Transmitter
BIT 5BIT 0 BIT 1
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
BIT 2 BIT 3 BIT 4 BIT 6 BIT 7
PARITY
OR DATA
BIT
PARITY
OR DATA
BIT
NEXT
START
BIT
NEXT
START
BIT
STOP
BIT
STOP
BIT
8-BIT DATA FORMAT
(BIT M IN SCC1 CLEAR)
9-BIT DATA FORMAT
(BIT M IN SCC1 SET)
START
BIT
START
BIT
PEN
PTY
H876543210L
11-BIT
TRANSMIT
STOP START
T8
SCTE
SCTIE
TCIE
SBK
TC
CGMXCLK OR BUS CLOCK
PARITY
GENERATION
MSB
ESCI DATA REGISTER
LOAD FROM SCDR SHIFT ENABLE
PREAMBLE
(ALL ONES)
BREAK
(ALL ZEROS)
TRANSMITTER
CONTROL LOGIC
SHIFT REGISTER
TC
SCTIE
TCIE
SCTE
TRANSMITTER CPU INTERRUPT REQUEST
M
ENSCI
LOOPS
TE
TXINV
INTERNAL BUS
÷ 4
PRE-
SCALER
SCP1
SCP0
SCR2
SCR1
SCR0
BAUD
DIVIDER
÷ 16
SCI_TxD
PRE-
SCALER
PDS1
PDS2
PDS0
PSSB3
PSSB4
PSSB2
PSSB1
PSSB0
LINT