Datasheet

Enhanced Serial Communications Interface (ESCI) Module
MC68HC908GR16 Data Sheet, Rev. 5.0
176 Freescale Semiconductor
Figure 14-21. Bit Time Measurement with ACLK = 0
Figure 14-22. Bit Time Measurement with ACLK = 1, Scenario A
Figure 14-23. Bit Time Measurement with ACLK = 1, Scenario B
14.9.4 Arbitration Mode
If AM[1:0] is set to 10, the arbiter module operates in arbitration mode. On every rising edge of SCI_TxD
(output of the ESCI module, internal chip signal), the counter is started. When the counter reaches $38
(ACLK = 0) or $08 (ACLK = 1), RxD is statically sensed. If in this case, RxD is sensed low (for example,
another bus is driving the bus dominant) ALOST is set. As long as ALOST is set, the TxD pin is forced
to 1, resulting in a seized transmission.
If SCI_TxD is sensed 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration
operation will be restarted after the next rising edge of SCI_TxD.
CPU WRITES SCIACTL
COUNTER STARTS,
COUNTER STOPS,
MEASURED TIME
CPU READS RESULT
RXD
WITH $20
ARUN = 1
AFIN = 1
OUT OF SCIADAT
CPU WRITES SCIACTL WITH $30
COUNTER STARTS, ARUN = 1
COUNTER STOPS, AFIN = 1
MEASURED TIME
CPU READS RESULT OUT
RXD
OF SCIADAT
CPU WRITES SCIACTL
COUNTER STARTS,
COUNTER STOPS,
MEASURED TIME
CPU READS RESULT
RXD
OUT OF SCIADAT
AFIN = 1
ARUN = 1
WITH $30