Datasheet

MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 177
Chapter 15
System Integration Module (SIM)
15.1 Introduction
This section describes the system integration module (SIM). Together with the central processor unit
(CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in
Figure 15-2. Table 15-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state
controller that coordinates CPU and exception timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Table 15-1 shows the internal signal names used in this section.
Table 15-1. Signal Name Conventions
Signal Name Description
CGMXCLK Buffered version of OSC1 from clock generator module (CGM)
CGMVCLK PLL output
CGMOUT
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
IAB Internal address bus
IDB Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W
Read/write signal