Datasheet

Development Support
MC68HC908GR16 Data Sheet, Rev. 5.0
238 Freescale Semiconductor
Figure 19-1. Break Module Block Diagram
19.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See 15.7.3 Break Flag Control Register and the Break Interrupts subsection
for each module.
Addr.Register Name Bit 7654321Bit 0
$FE00
Break Status Register
(BSR)
See page 241.
Read:
RRRRRR
SBSW
R
Write: Note
(1)
Reset: 0
$FE02
Break Auxiliary Register
(BRKAR)
See page 240.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:00000000
$FE03
Break Flag Control
Register (BFCR)
See page 241.
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE09
Break Address High
Register (BRKH)
See page 240.
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:00000000
$FE0A
Break Address Low
Register (BRKL)
See page 240.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:00000000
$FE0B
Break Status and Control
Register (BRKSCR)
See page 239.
Read:
BRKE BRKA
000000
Write:
Reset:00000000
1. Writing a 0 clears SBSW.
= Unimplemented R = Reserved
Figure 19-2. Break I/O Register Summary
ADDRESS BUS[15:8]
ADDRESS BUS[7:0]
8-BIT COMPARATOR
8-BIT COMPARATOR
CONTROL
BREAK ADDRESS REGISTER LOW
BREAK ADDRESS REGISTER HIGH
ADDRESS BUS[15:0]
BKPT
(TO SIM)