Datasheet

Break Module (BRK)
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 239
19.2.1.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
19.2.1.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
19.2.1.4 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
19.2.2 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status register (BSR)
• Break flag control register (BFCR)
19.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to
bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = Break address match
0 = No break address match
Address:
$FE0B
Bit 7654321Bit 0
Read:
BRKE BRKA
000000
Write:
Reset:00000000
= Unimplemented
Figure 19-3. Break Status and Control Register (BRKSCR)