Datasheet

Monitor ROM (MON)
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 245
Figure 19-12. Forced Monitor Mode Circuit (IRQ = GND)
Enter monitor mode with pin configuration shown in Table 19-1 by pulling RST
low and then high. The
rising edge of RST
latches monitor mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security bytes (see
19.3.2 Security). After the security bytes, the MCU sends a break signal (10 consecutive 0s) to the host,
indicating that it is ready to receive a command.
19.3.1.1 Normal Monitor Mode
Table 19-1 shows the pin conditions for entering monitor mode.
If V
TST
is applied to IRQ and PTB4 is low upon monitor mode entry, the bus frequency is a divide-by-two
of the input clock. If PTB4 is high with V
TST
applied to IRQ upon monitor mode entry, the bus frequency
will be a divide-by-four of the input clock. Holding the PTB4 pin low when entering monitor mode causes
a bypass of a divide-by-two stage at the oscillator only if V
TST
is applied to IRQ. In this event, the
CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal
bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.
When monitor mode was entered with V
TST
on IRQ, the computer operating properly (COP) is disabled
as long as V
TST
is applied to either IRQ or RST.
10 k
RST
IRQ
PTA0
OSC1
8
7
DB9
2
3
5
16
15
2
6
10
9
V
DD
C5
MAX232
V+
V–
V
DD
C4
+
1
2
3
4
5
6
74HC125
74HC125
10 kΩ
V
SS
0.1 μF
V
DD
C1+
C1–
5
4
1 μF
C2+
C2–
+
3
1
1 μF
+
+
+
C3
V
DD
N.C.
V
CC
GND
OSC2
33 pF
15 pF
32.768 kHz
10 MΩ
V
DDA
PTB4
PTB0
PTB1
PTA1
V
SSA
MC68HC908GR16
N.C.
N.C.
N.C.
10 k
4.7 k