Datasheet
Monitor ROM (MON)
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 247
This condition states that as long as V
TST
is maintained on the IRQ pin after entering monitor mode, or if
V
TST
is applied to RST after the initial reset to get into monitor mode (when V
TST
was applied to IRQ),
then the COP will be disabled. In the latter situation, after V
TST
is applied to the RST pin, V
TST
can be
removed from the IRQ
pin in the interest of freeing the IRQ for normal functionality in monitor mode.
19.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ
, then all port B pin requirements and conditions,
including the PTB4 frequency divisor selection, are not in effect. This is to reduce circuit requirements
when performing in-circuit programming.
NOTE
Once the reset vector has been programmed, the traditional method of
applying a voltage, V
TST
, to IRQ must be used to enter monitor mode.
An external oscillator of 9.8304 MHz is required for a baud rate of 9600, as the internal bus frequency is
automatically set to the external frequency divided by four.
When the forced monitor mode is entered the COP is always disabled regardless of the state of IRQ
or
RST
.
19.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
Table 19-2 summarizes the differences between user mode and monitor mode.
19.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
Figure 19-13. Monitor Data Format
Table 19-2. Mode Differences
Modes
Functions
Reset
Vector High
Reset
Vector Low
Break
Vector High
Break
Vector Low
SWI
Vector High
SWI
Vector Low
User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD
BIT 5
START
BIT
BIT 1
NEXT
STOP
BIT
START
BIT
BIT 2 BIT 3 BIT 4 BIT 7BIT 0
BIT 6