Datasheet

Electrical Specifications
MC68HC908GR16 Data Sheet, Rev. 5.0
256 Freescale Semiconductor
Monitor mode entry voltage
V
TST
V
DD
+ 2.5
—
V
DD
+ 4.0
V
Low-voltage inhibit, trip falling voltage
V
TRIPF
3.9 4.25 4.50 V
Low-voltage inhibit, trip rising voltage
V
TRIPR
4.2 4.35 4.60 V
Low-voltage inhibit reset/recover hysteresis
(V
TRIPF
+ V
HYS
= V
TRIPR
)
V
HYS
—60 —mV
POR rearm voltage
(8)
V
POR
0 — 100 mV
POR reset voltage
(9)
V
PORRST
0 700 800 mV
POR rise time ramp rate
(10)
R
POR
0.035 — — V/ms
1. V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= T
A
(min) to T
A
(max), unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) I
DD
measured using external square wave clock source (f
OSC
= 32 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run I
DD
. Measured with all modules enabled.
4. Wait I
DD
measured using external square wave clock source (f
OSC
= 32 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
DD
.
Measured with CGM and LVI enabled.
5. Stop I
DD
is measured with OSC1 = V
SS
.
6. Stop I
DD
with TBM enabled is measured using an external square wave clock source (f
OSC
= 32 MHz). All inputs 0.2 V from
rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled. Port B leakage is specified in 20.10 5.0-Volt ADC Characteristics.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum V
DD
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
DD
is reached.
Characteristic
(1)
Symbol Min
Typ
(2)
Max Unit