Datasheet

5.0-Volt Control Timing
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 259
20.7 5.0-Volt Control Timing
20.8 3.3-Volt Control Timing
Figure 20-1. RST and IRQ Timing
Characteristic
(1)
1. V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
DD
unless otherwise noted.
Symbol Min Max Unit
Frequency of operation
Crystal option
External clock option
(2)
2. No more than 10% duty cycle deviation from 50%.
f
OSC
32
dc
100
32.8
kHz
MHz
Internal operating frequency
f
OP
(f
Bus
)
—8.2MHz
Internal clock period (1/f
OP
)t
CYC
122 — ns
RESET input pulse width low
(3)
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
t
IRL
50 — ns
IRQ
interrupt pulse width low
(4)
(edge-triggered)
4. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
t
ILIH
50 — ns
IRQ
interrupt pulse period
t
ILIL
Note 5 —
t
CYC
Characteristic
(1)
1. V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
DD
unless otherwise noted.
Symbol Min Max Unit
Frequency of operation
Crystal option
External clock option
(2)
2. No more than 10% duty cycle deviation from 50%.
f
OSC
32
dc
100
16.4
kHz
MHz
Internal operating frequency
f
OP
(f
Bus
)
—4.1MHz
Internal clock period (1/f
OP
)t
CYC
244 — ns
RESET input pulse width low
(3)
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
t
IRL
125 — ns
IRQ
interrupt pulse width low
(4)
(edge-triggered)
4. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
t
ILIH
125 — ns
IRQ
interrupt pulse period
t
ILIL
Note 5 —
t
CYC
RST
IRQ
t
RL
t
ILIH
t
ILIL