Datasheet

Input/Output (I/O) Section
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 29
$FE10 UNIMPLEMENTED
16 BYTES
RESERVED FOR COMPATIBILITY WITH MONITOR CODE
FOR A-FAMILY PART
↓
$FE1F
$FE20
MONITOR ROM
350 BYTES
↓
$FF7D
$FF7E FLASH BLOCK PROTECT REGISTER (FLBPR)
$FF7F
UNIMPLEMENTED
85 BYTES
↓
$FFD3
$FFD4
FLASH VECTORS
44 BYTES
↓
$FFFF
(1)
1. $FFF6–$FFFD used for eight security bytes
Addr.Register Name Bit 7654321Bit 0
$0000
Port A Data Register
(PTA)
See page 124.
Read:
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
Write:
Reset: Unaffected by reset
$0001
Port B Data Register
(PTB)
See page 126.
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
$0002
Port C Data Register
(PTC)
See page 128.
Read: 0
PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
Write:
Reset: Unaffected by reset
$0003
Port D Data Register
(PTD)
See page 130.
Read:
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write:
Reset: Unaffected by reset
$0004
Data Direction Register A
(DDRA)
See page 124.
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
$0005
Data Direction Register B
(DDRB)
See page 126.
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
Figure 2-1. Memory Map (Continued)