Datasheet

Revision History
MC68HC908GR16 Data Sheet, Rev. 5.0
4 Freescale Semiconductor
September,
2004
2.0
Figure 1-1. MCU Block Diagram — Removed data bus switch module 22
Figure 2-2. Control, Status, and Data Registers and Figure 5-1. Configuration
Register 2 (CONFIG2) — Changed name of bit 0 from SCIBDSRC to
ESCIBDSRC
29
and
78
14.8.8 ESCI Prescaler Register — Updated description in this subsection 168
14.9.1 ESCI Arbiter Control Register — Updated description of ACLK bit 172
14.9.3 Bit Time Measurement — Updated bit time measurement mode for
ACLK = 0
173
Added dc injection current values to:
20.5 5.0-Vdc Electrical Characteristics
20.6 3.3-Vdc Electrical Characteristics
253
255
20.9.1 CGM Component Specifications — Corrected series resistor values 258
20.15 Memory Characteristics — Table updated to reflect new values 265
March,
2005
3.0
10.5 Clock Generator Module (CGM) — Updated description to remove
erroneous information.
112
20.9 Clock Generation Module Characteristics — Updated to reflect correct
values.
260
January,
2007
4.0
Table 13-2. Interrupt Source Flags — Changed IF7 to TIM2 channel instead
of Reserved.
144
Table 2-1. Vector Addresses — Changed address $FFEE to TIM2 Channel 1
Vector (High) and $FFEF to TIM2 Channel 1 Vector (Low) from Reserved
37
Figure 2-2. Control, Status, and Data Registers — Changed addresses
$0033 to $0035 to show TIM2 Channel 1 registers.
29
April,
2007
5.o
Figure 2-2. Control, Status, and Data Registers — Replaced TMCLKSEL with
TMBCLKSEL to be compatile with development tool nomenclature
32
Chapter 5 Configuration Register (CONFIG) — Changed COPCLK to
CGMXCLK, replaced TMCLKSEL with TMBCLKSEL to be compatible with
development tool nomenclature, and replaced exponents for COP timeout
period
79
6.2 Functional Description — Replaced exponents for COP timeout period 84
10.6.2 Stop Mode — Changed COPCLK to CGMXCLK 113
Figure 14-2. ESCI Module Block Diagram — Replaced BUS_CLK with BUS
CLOCK and removed reference to rx BUSCLK
149
Figure 14-5. ESCI Transmitter and Figure 14-6. ESCI Receiver Block
Diagram — Added CGMXCLK OR to BUS CLOCK designator
151
154
14.8.7 ESCI Baud Rate Register — Replaced description of the LINT and
LINR bits
169
Figure 17-1 . Timebase Block Diagram and 17.5 TBM Interrupt Rate—
Replaced TBMCLKSEL with TMBCLKSEL to be compatible with
development tool nomenclature
218
219
Revision History (Continued)
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Revision
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