Datasheet

Functional Description
MC68HC908GR16 Data Sheet, Rev. 5.0
Freescale Semiconductor 65
9. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, f
VRS
. The
center-of-range frequency is the midpoint between the minimum and maximum frequencies
attainable by the PLL.
For proper operation,
10. Verify the choice of P, R, N, E, and L by comparing f
VCLK
to f
VRS
and f
VCLKDES
. For proper
operation, f
VCLK
must be within the application’s tolerance of f
VCLKDES
, and f
VRS
must be as close
as possible to f
VCLK
.
NOTE
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
11. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P.
b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E.
c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high
(PMSH), program the binary equivalent of N.
d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program the binary coded equivalent
of R.
Table 4-1 provides numeric examples (numbers are in hexadecimal notation):
Table 4-1. Numeric Example
f
BUS
f
RCLK
RNPEL
2.0 MHz 32.768 kHz 1 F5 0 0 D1
2.4576 MHz 32.768 kHz 1 12C 0 1 80
2.5 MHz 32.768 kHz 1 132 0 1 83
4.0 MHz 32.768 kHz 1 1E9 0 1 D1
4.9152 MHz 32.768 kHz 1 258 0 2 80
5.0 MHz 32.768 kHz 1 263 0 2 82
7.3728 MHz 32.768 kHz 1 384 0 2 C0
8.0 MHz 32.768 kHz 1 3D1 0 2 D0
f
VRS
L2
E
×()f
NOM
=
f
VRS
f
VCLK
–
f
NOM
2
E
×
2
--------------------------
≤