MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A Data Sheet M68HC08 Microcontrollers MC68HC908GR60A Rev. 5 04/2007 freescale.
MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004, 2006, 2007.
Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level April, 2004 N/A July, 2004 1 June, 2005 March, 2006 July, 2006 April, 2007 2 3 4 5 Page Number(s) Description Initial release N/A 9.7.3 Keyboard Interrupt Polarity Register — Corrected description of KBIP7–KBIP0. 119 Table 13-6.
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Chapters MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev.
Table of Contents Chapter 1 General Description 1.1 1.2 1.2.1 1.2.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 1.5.13 1.5.14 1.5.15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Features . . . . . . . . . . . . . . . . .
Table of Contents 2.6.6 FLASH-1 Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 4 Clock Generator Module (CGM) 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 4.4.10 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.6 4.7 4.7.1 4.7.2 4.7.3 4.8 4.8.1 4.8.2 4.8.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents Chapter 6 Computer Operating Properly (COP) Module 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.4 6.5 6.6 6.7 6.7.1 6.7.2 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 9 Keyboard Interrupt Module (KBI) 9.1 9.2 9.3 9.4 9.5 9.5.1 9.5.2 9.6 9.7 9.7.1 9.7.2 9.7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 10.10 Enhanced Serial Communications Interface Module (ESCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.11 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6 12.6.1 12.6.2 12.6.3 12.7 12.7.1 12.7.2 12.8 12.8.1 12.8.2 12.9 12.9.1 12.9.2 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 13.8.3 ESCI Control Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.4 ESCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.5 ESCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8.6 ESCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 15 Serial Peripheral Interface (SPI) Module 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1 Master Mode . . . . . . .
Table of Contents Chapter 17 Timer Interface Module (TIM1) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.
18.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.7.1 TIM2 Clock Pin (T2CH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.7.2 TIM2 Channel I/O Pins (T2CH5:T2CH2 and T2CH1:T2CH0) . . . . . . . . . . . . . . . . . . . . . . 18.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 20.9 20.9.1 20.9.2 20.9.3 20.10 20.11 20.12 20.13 20.14 20.15 Clock Generation Module (CGM) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Component Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . . . . .
Chapter 1 General Description 1.1 Introduction The MC68HC908GR60A, MC68HC908GR48A, and MC68HC908GR32A are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
General Description • • • • • • • • • • • • • • • • • • • • Master reset pin and power-on reset (POR) On-chip FLASH memory: – MC68HC908GR60A — 60 Kbytes – MC68HC908GR48A — 48 Kbytes – MC68HC908GR32A — 32 Kbytes Random-access memory (RAM): – MC68HC908GR60A — 2048 bytes – MC68HC908GR48A — 1536 bytes – MC68HC908GR32A — 1536 bytes Serial peripheral interface (SPI) module Enhanced serial communications interface (ESCI) module One 16-bit, 2-channel timer interface module (TIM1) with selectable input captur
MCU Block Diagram • • Specific features in 48-pin LQFP are: – Port A is 8 bits: PTA0–PTA7; shared with ADC and KBI modules – Port B is 8 bits: PTB0–PTB7; shared with ADC module – Port C is only 7 bits: PTC0–PTC6 – Port D is 8 bits: PTD0–PTD7; shared with SPI, TIM1, and TIM2 modules – Port E is only 6 bits: PTE0–PTE5; shared with ESCI module Specific features in 64-pin QFP are: – Port A is 8 bits: PTA0–PTA7; shared with ADC and KBI modules – Port B is 8 bits: PTB0–PTB7; shared with ADC module – Port C is
General Description INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE VSSAD/VREFL 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2
Pin Assignments 1.4 Pin Assignments CGMXFC VSSA VDDA PTC1 PTC0 PTA3/KBD3/AD11 30 29 28 27 26 25 1 OSC2 RST 31 32 OSC1 Figure 1-2, Figure 1-3, and Figure 1-4 illustrate the pin assignments for the 32-pin LQFP, 48-pin LQFP, and 64-pin QFP respectively.
37 PTA3/KBD3/AD11 PTA4/KBD4/AD12 PTA7/KBD7/AD15 41 38 PTC0 42 PTA5/KBD5/AD13 PTC1 43 39 VDDA 44 PTA6/KBD6/AD14 VSSA 45 40 CGMXFC RST 1 46 OSC2 47 48 OSC1 General Description 36 PTA2/KBD2/AD10 PTE5 7 30 VDDAD/VREFH IRQ 8 29 PTB7/AD7 PTD0/SS/MCLK 9 28 PTB6/AD6 PTD1/MISO 10 27 PTB5/AD5 PTD2/MOSI 11 26 PTB4/AD4 25 PTB3/AD3 PTB2/AD2 24 VSS 13 PTD3/SPSCK 12 23 VSSAD/VREFL PTB1/AD1 31 22 6 PTB0/AD0 PTE4 21 PTC5 PTC4 32 20 5 PTC3 PTE3 19 PTC6 PTC2 33 18
CGMXFC VSSA VDDA PTC1 PTC0 PTG7/AD23 PTG6/AD22 PTG5/AD21 PTG4/AD20 PTA7/KBD7/AD15 PTA6/KBD6/AD14 PTA5/KBD5/AD13 PTA4/KBD4/AD12 63 62 61 60 59 58 57 56 55 54 53 52 51 50 64 RST PTA3/KBD3/AD11 OSC2 OSC1 Pin Functions 49 48 PTA2/KBD2/AD10 1 PTE0/TxD 2 47 PTA1/KBD1/AD9 PTE1/RxD 3 46 PTA0/KBD0/AD8 PTE2 4 45 PTC6 PTE3 5 44 PTC5 PTE4 6 43 PTG3/AD19 PTE5 7 42 PTG2/AD18 PTF0 8 41 PTG1/AD17 PTF1 9 40 PTG0/AD16 PTF2 10 39 VSSAD/VREFL PTF3 11 38 V
General Description MCU VSS VDD C1 0.1 μF + C2 VDD Note: Component values shown represent typical applications. Figure 1-5. Power Supply Bypassing 1.5.2 Oscillator Pins (OSC1 and OSC2) OSC1 and OSC2 are the connections for an external crystal, resonator, or clock circuit. See Chapter 4 Clock Generator Module (CGM). 1.5.3 External Reset Pin (RST) A low on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system.
Pin Functions VREFL is the low reference supply for the ADC, and by default the VSSAD/VREFL pin should be connected to the same voltage potential as VSS. See Chapter 3 Analog-to-Digital Converter (ADC). 1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7/AD15–PTA0/KBD0/AD8) PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be programmed to serve as keyboard interrupt pins or used as analog-to-digital inputs.
General Description PTF3–PTF0 are general-purpose, bidirectional I/O port pins that contain higher current sink/source capability. PTF7–PTF0 are only available on the 64-pin QFP package. See Chapter 17 Timer Interface Module (TIM1), Chapter 18 Timer Interface Module (TIM2), and Chapter 12 Input/Output (I/O) Ports. 1.5.14 Port G I/O Pins (PTG7/AD23–PTBG0/AD16) PTG7–PTG0 are general-purpose, bidirectional I/O port pins that can also be used for analog-to-digital converter (ADC) inputs.
Chapter 2 Memory 2.1 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 62,078 bytes of user FLASH memory • 2048 bytes of random-access memory (RAM) • 52 bytes of user-defined vectors 2.2 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset. In the memory map (Figure 2-1) and in register figures in this document, unimplemented locations are shaded. 2.
Memory $0000 ↓ $003F I/O REGISTERS 64 BYTES $0040 ↓ $043F RAM-1 1024 BYTES $0440 ↓ $0461 I/O REGISTERS 34 BYTES $0462 ↓ $04FF FLASH-2 158 BYTES $0500 ↓ $057F RESERVED 128 BYTES $FE00 SIM BREAK STATUS REGISTER (BSR) $FE01 SIM RESET STATUS REGISTER (SRSR) $FE02 RESERVED $FE03 SIM BREAK FLAG CONTROL REGISTER (BFCR) $FE04 INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 INTERRUPT STATUS REGISTER 4 (INT4) $FE08
Input/Output (I/O) Section Addr. $0000 Register Name Port A Data Register Read: (PTA) Write: See page 135. Reset: $0001 Port B Data Register Read: (PTB) Write: See page 138. Reset: $0002 Port C Data Register Read: (PTC) Write: See page 140. Reset: $0003 $0004 Port D Data Register Read: (PTD) Write: See page 142. Reset: Data Direction Register A Read: (DDRA) Write: See page 136. Reset: $0005 Data Direction Register B Read: (DDRB) Write: See page 138.
Memory Addr. $000C $000D $000E $000F $0010 $0011 $0012 Register Name Data Direction Register E Read: (DDRE) Write: See page 146. Reset: Port C Input Pullup Enable Read: Register (PTCPUE) Write: See page 142. Reset: SPI Control Register Read: (SPCR) Write: See page 217. Reset: SPI Status and Control Read: Register (SPSCR) Write: See page 218. Reset: SPI Data Register Read: (SPDR) Write: See page 220. Reset: $0014 ESCI Control Register 2 Read: (SCC2) Write: See page 168.
Input/Output (I/O) Section Addr. $0018 $0019 Register Name ESCI Data Register Read: (SCDR) Write: See page 173. Reset: ESCI Baud Rate Register Read: (SCBR) Write: See page 174. Reset: Keyboard Status and Control Read: $001A Register (INTKBSCR) Write: See page 118. Reset: $001B Keyboard Interrupt Enable Read: Register (INTKBIER) Write: See page 119. Reset: $001C Timebase Module Control Read: Register (TBCR) Write: See page 224.
Memory Addr. $0024 $0025 $0026 Register Name TIM1 Counter Modulo Read: Register Low (T1MODL) Write: See page 236. Reset: TIM1 Channel 0 Status and Read: Control Register (T1SC0) Write: See page 237. Reset: TIM1 Channel 0 Read: Register High (T1CH0H) Write: See page 240. Reset: $0027 TIM1 Channel 0 Read: Register Low (T1CH0L) Write: See page 240. Reset: $0028 TIM1 Channel 1 Status and Read: Control Register (T1SC1) Write: See page 237.
Input/Output (I/O) Section Addr. $0030 $0031 $0032 Register Name Bit 7 TIM2 Channel 0 Status and Read: Control Register (T2SC0) Write: See page 237. Reset: TIM2 Channel 0 Read: Register High (T2CH0H) Write: See page 240. Reset: TIM2 Channel 0 Read: Register Low (T2CH0L) Write: See page 240. Reset: $0033 TIM2 Channel 1 Status and Read: Control Register (T2SC1) Write: See page 237. Reset: $0034 TIM2 Channel 1 Read: Register High (T2CH1H) Write: See page 240.
Memory Addr. $003C $003D $003E Register Name 6 5 4 3 2 1 Bit 0 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 0 1 1 1 1 1 ADC Data High Register Read: (ADRH) Write: See page 67. Reset: 0 0 0 0 0 0 AD9 AD8 ADC Data Low Register Read: (ADRL) Write: See page 67. Reset: AD7 AD2 AD1 AD0 COCO $003F ADC Clock Register Read: (ADCLK) Write: See page 69. Reset: $0440 Port F Data Register Read: (PTF) Write: See page 147.
Input/Output (I/O) Section Addr. $0459 $045A $045B Register Name Bit 7 TIM2 Channel 3 Status and Read: Control Register (T2SC3) Write: See page 255. Reset: TIM2 Channel 3 Read: Register High (T2CH3H) Write: See page 258. Reset: TIM2 Channel 3 Read: Register Low (T2CH3L) Write: See page 258. Reset: $045C TIM2 Channel 4 Status and Read: Control Register (T2SC4) Write: See page 255. Reset: $045D TIM2 Channel 4 Read: Register High (T2CH4H) Write: See page 258.
Memory Addr. Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 0 0 0 0 0 0 0 Interrupt Status Register 1 Read: (INT1) Write: See page 195. Reset: IF6 IF5 IF4 IF3 IF2 IF1 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Interrupt Status Register 2 Read: (INT2) Write: See page 195.
Input/Output (I/O) Section Addr. Register Name $FF80 FLASH-1 Block Protect Read: Register (FL1BPR)(1) Write: See page 43. Reset: $FF81 FLASH-2 Block Protect Read: Register (FL2BPR)(1) Write: See page 51. Reset: Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 BPR2 BPR1 BPR0 HVEN MASS ERASE PGM 0 0 0 0 Unaffected by reset BPR7 BPR6 BPR5 BPR4 BPR3 Unaffected by reset 1.
Memory Table 2-1.
Random-Access Memory (RAM) 2.5 Random-Access Memory (RAM) The RAM locations are broken into two non-continuous memory blocks. The RAM addresses locations are $0040–$043F and $0580–$097F. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 192 bytes of RAM.
Memory Programming tools are available from Freescale Semiconductor. Contact your local representative for more information. NOTE A security feature prevents viewing of the FLASH contents.(1) 2.6.2 FLASH-1 Control and Block Protect Registers The FLASH-1 array has two registers that control its operation, the FLASH-1 control register (FL1CR) and the FLASH-1 block protect register (FL1BPR). 2.6.2.1 FLASH-1 Control Register The FLASH-1 control register (FL1CR) controls FLASH program and erase operations.
FLASH-1 Memory (FLASH-1) 2.6.2.2 FLASH-1 Block Protect Register The FLASH-1 block protect register (FL1BPR) is implemented as a byte within the FLASH-1 memory; therefore, it can only be written during a FLASH programming sequence. The value in this register determines the starting location of the protected range within the FLASH-1 memory. Address: $FF80 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Unaffected by reset Figure 2-4.
Memory Decreasing the value in FL1BPR by one increases the protected range by one page (128 bytes). However, programming the block protect register with $FE protects a range twice that size, 256 bytes, in the corresponding array. $FE means that locations $FF00–$FFFF are protected in FLASH-1. The FLASH memory does not exist at some locations. The block protection range configuration is unaffected if FLASH memory does not exist in that range.
FLASH-1 Memory (FLASH-1) 2.6.4 FLASH-1 Mass Erase Operation Use this step-by-step procedure to erase the entire FLASH-1 memory: 1. Set both the ERASE bit and the MASS bit in the FLASH-1 control register (FL1CR). 2. Read the FLASH-1 block protect register (FL1BPR). NOTE Mass erase is disabled whenever any block is protected (FL1BPR does not equal $FF). 3. 4. 5. 6. 7. 8. 9. 10. Write to any FLASH-1 address within the FLASH-1 array with any data. Wait for a time, tNVS (minimum 10 μs). Set the HVEN bit.
Memory 2.6.5 FLASH-1 Page Erase Operation Use this step-by-step procedure to erase a page (128 bytes) of FLASH-1 memory: 1. Set the ERASE bit and clear the MASS bit in the FLASH-1 control register (FL1CR). 2. Read the FLASH-1 block protect register (FL1BPR). 3. Write any data to any FLASH-1 address within the address range of the page (128 byte block) to be erased. 4. Wait for time, tNVS (minimum 10 μs). 5. Set the HVEN bit. 6. Wait for time, tERASE (minimum 1 ms or 4 ms). 7. Clear the ERASE bit. 8.
FLASH-1 Memory (FLASH-1) 2.6.6 FLASH-1 Program Operation Programming of the FLASH-1 memory is done on a row basis. A row consists of 64 consecutive bytes with address ranges as follows: • $XX00 to $XX3F • $XX40 to $XX7F • $XX80 to $XXBF • $XXC0 to $XXFF During the programming cycle, make sure that all addresses being written to fit within one of the ranges specified above. Attempts to program addresses in different row ranges in one programming cycle will fail.
Memory E. The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing the PGM bit (step 7 to step 10) must not exceed the maximum programming time, tPROG maximum. F. Be cautious when programming the FLASH-1 array to ensure that non-FLASH locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. 2.6.
FLASH-1 Memory (FLASH-1) Algorithm for programming a row (64 bytes) of FLASH memory 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 WAIT FOR A TIME, tNVS 5 SET HVEN BIT 6 WAIT FOR A TIME, tPGS 7 8 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME, tPROG COMPLETED PROGRAMMING THIS ROW? YES NO NOTES: The time between each FLASH address change (step 7 to step 7) or the time between the last FL
Memory 2.7 FLASH-2 Memory (FLASH-2) This subsection describes the operation of the embedded FLASH-2 memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. 2.7.1 Functional Description The FLASH-2 memory is a non-continuous array consisting of a total of 29,822 bytes. An erased bit reads as a 1 and a programmed bit reads as a 0.
FLASH-2 Memory (FLASH-2) HVEN — High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS — Mass Erase Control Bit Setting this read/write bit configures the FLASH-2 array for mass or page erase operation.
Memory 16-BIT MEMORY ADDRESS START ADDRESS OF FLASH BLOCK PROTECT 0 FLBPR VALUE 0 0 0 0 0 0 0 Figure 2-9. FLASH-2 Block Protect Start Address Table 2-3.
FLASH-2 Memory (FLASH-2) When bits within FL2BPR are programmed (0), they lock a block of memory address ranges as shown in 2.7.2.2 FLASH-2 Block Protect Register. If FL2BPR is programmed with any value other than $FF, the protected block of FLASH memory can not be erased or programmed. NOTE The vector locations and the FLASH block protect registers are located in the same page. FL1BPR and FL2BPR are not protected with special hardware or software.
Memory 2.7.5 FLASH-2 Page Erase Operation Use this step-by-step procedure to erase a page (128 bytes) of FLASH-2 memory: 1. Set the ERASE bit and clear the MASS bit in the FLASH-2 control register (FL2CR). 2. Read the FLASH-2 block protect register (FL2BPR). 3. Write any data to any FLASH-2 address within the address range of the page (128 byte block) to be erased. 4. Wait for time, tNVS (minimum 10 μs). 5. Set the HVEN bit. 6. Wait for time, tERASE (minimum 1 ms or 4 ms). 7. Clear the ERASE bit. 8.
FLASH-2 Memory (FLASH-2) 2.7.6 FLASH-2 Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes with address ranges as follows: • $XX00 to $XX3F • $XX40 to $XX7F • $XX80 to $XXBF • $XXC0 to $XXFF During the programming cycle, make sure that all addresses being written to fit within one of the ranges specified above. Attempts to program addresses in different row ranges in one programming cycle will fail.
Memory E. The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing the PGM bit (step 7 to step 10) must not exceed the maximum programming time, tPROG maximum. F. Be cautious when programming the FLASH-2 array to ensure that non-FLASH locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. 2.7.
FLASH-2 Memory (FLASH-2) Algorithm for programming a row (64 bytes) of FLASH memory 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 WAIT FOR A TIME, tNVS 5 SET HVEN BIT 6 WAIT FOR A TIME, tPGS 7 8 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME, tPROG COMPLETED PROGRAMMING THIS ROW? YES NO NOTES: The time between each FLASH address change (step 7 to step 7) or the time between the last FL
Memory MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev.
Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the 10-bit analog-to-digital converter (ADC). 3.2 Features Features of the ADC module include: • 24 channels with multiplexed input • Linear successive approximation with monotonicity • 10-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock • Left or right justified result • Left justified sign data mode 3.
Analog-to-Digital Converter (ADC) INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE VSSAD/VREFL SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/SS/MCLK(2) PTE5–P
Functional Description INTERNAL DATA BUS READ DDRx WRITE DDRx DISABLE DDRx RESET WRITE PTx PTx PTx ADC CHANNEL x READ PTx DISABLE ADC DATA REGISTER INTERRUPT LOGIC AIEN CONVERSION COMPLETE ADC ADC VOLTAGE IN (VADIN) CHANNEL SELECT ADCH4–ADCH0 ADC CLOCK COCO CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV2–ADIV0 ADICLK Figure 3-2. ADC Block Diagram 3.3.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $3FF (full scale).
Analog-to-Digital Converter (ADC) 3.3.3 Conversion Time Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency. Conversion time = 16 to 17 ADC cycles ADC frequency Number of bus cycles = conversion time × bus frequency 3.3.4 Conversion In continuous conversion mode, the ADC data register will be filled with new data after each conversion.
Monotonicity NOTE Quantization error is affected when only the most significant eight bits are used as a result. See Figure 3-3. 8-BIT 10-BIT RESULT RESULT IDEAL 8-BIT CHARACTERISTIC WITH QUANTIZATION = ±1/2 10-BIT TRUNCATED TO 8-BIT RESULT 003 00B 00A 009 002 IDEAL 10-BIT CHARACTERISTIC WITH QUANTIZATION = ±1/2 008 007 006 005 001 004 WHEN TRUNCATION IS USED, ERROR FROM IDEAL 8-BIT = 3/8 LSB DUE TO NON-IDEAL QUANTIZATION.
Analog-to-Digital Converter (ADC) down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the WAIT instruction. 3.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. 3.
I/O Registers 3.7.4 ADC Voltage Reference Low Pin (VREFL) The ADC analog portion uses VREFL as its lower voltage reference pin. By default, connect the VREFL pin to the same voltage potential as VSS. External filtering is often necessary to ensure a clean VREFL for good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values.
Analog-to-Digital Converter (ADC) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion.
I/O Registers Table 3-1. Mux Channel Select(1) (Continued) ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select 1 0 0 0 0 PTG0/AD16 1 0 0 0 1 PTG1/AD17 1 0 0 1 0 PTG2/AD18 1 0 0 1 1 PTG3/AD19 1 0 1 0 0 PTG4/AD20 1 0 1 0 1 PTG5/AD21 1 0 1 1 0 PTG6/AD22 1 0 1 1 1 PTG7/AD23 1 ↓ 1 1 ↓ 1 0 ↓ 1 0 ↓ 0 0 ↓ 0 Unused 1 1 1 0 1 VREFH 1 1 1 1 0 VREFL 1 1 1 1 1 ADC power off 1.
Analog-to-Digital Converter (ADC) 3.8.2.2 Right Justified Mode In right justified mode, the ADRH register holds the two MSBs of the 10-bit result. All other bits read as 0. The ADRL register holds the eight LSBs of the 10-bit result. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
I/O Registers 3.8.2.4 Eight Bit Truncation Mode In 8-bit truncation mode, the ADRL register holds the eight MSBs of the 10-bit result. The ADRH register is unused and reads as 0. The ADRL register is updated each time an ADC single channel conversion completes. In 8-bit mode, the ADRL register contains no interlocking with ADRH.
Analog-to-Digital Converter (ADC) ADICLK — ADC Input Clock Select Bit ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK) as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. 1 = Internal bus clock 0 = Oscillator output clock (CGMXCLK) The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock source is not fast enough, the ADC will generate incorrect conversions. See 20.10 5.
Chapter 4 Clock Generator Module (CGM) 4.1 Introduction This section describes the clock generator module. The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
Clock Generator Module (CGM) OSCILLATOR (OSC) OSC2 CGMXCLK (TO: SIM, TBM, ADC) OSC1 SIMOSCEN (FROM SIM) OSCENINSTOP (FROM CONFIG) PHASE-LOCKED LOOP (PLL) CGMRCLK CLOCK SELECT CIRCUIT BCS VDDA CGMXFC ÷2 A CGMOUT B S* (TO SIM) SIMDIV2 (FROM SIM) *WHEN S = 1, VSSA CGMOUT = B VPR1–VPR0 VRS7–VRS0 PHASE DETECTOR VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER CGMVCLK PLL ANALOG LOCK DETECTOR LOCK AUTOMATIC MODE CONTROL AUTO ACQ CGMINT INTERRUPT CONTROL PLLIE (TO SIM) PLLF MUL11–MUL0 CGMVD
Functional Description 4.3.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCENINSTOP bit in the CONFIG register enable the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency.
Clock Generator Module (CGM) 4.3.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. (See 4.5.
Functional Description The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 4.8 Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL control register (PCTL).
Clock Generator Module (CGM) In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Chapter 20 Electrical Specifications. After choosing N, the actual bus frequency can be determined using equation in 2 above. 4. Select a VCO frequency multiplier, N.
Functional Description 11. Program the PLL registers accordingly: a. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E. b. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N. If using a 1–8 MHz reference, the PMSL register must be reprogrammed from the reset value before enabling the PLL. c. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
Clock Generator Module (CGM) 4.3.9 CGM External Connections In its typical configuration, the CGM requires external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 4-2. Figure 4-2 shows only the logical representation of the internal components and may not represent actual circuitry.
I/O Signals 4.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 4.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 4.4.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure 4-2.
Clock Generator Module (CGM) 4.4.9 CGM Base Clock Output (CGMOUT) CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two. 4.4.10 CGM CPU Interrupt (CGMINT) CGMINT is the interrupt signal generated by the PLL lock detector. 4.
CGM Registers 4.5.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: Write: Reset: PLLIE 0 6 PLLF 5 4 3 2 1 Bit 0 PLLON BCS R R VPR1 VPR0 1 0 0 0 0 0 R = Reserved 0 = Unimplemented Figure 4-4.
Clock Generator Module (CGM) if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See 4.3.8 Base Clock Selector Circuit.). VPR1 and VPR0 — VCO Power-of-Two Range Select Bits These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction with L controls the hardware center-of-range frequency, fVRS.
CGM Registers LOCK — Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as 0 and has no meaning. The write one function of this bit is reserved for test, so this bit must always be written as a 0. Reset clears the LOCK bit.
Clock Generator Module (CGM) 4.5.4 PLL Multiplier Select Register Low The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider. Address: Read: Write: Reset: $0038 Bit 7 6 5 4 3 2 1 Bit 0 MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 0 1 0 0 0 0 0 0 Figure 4-7.
Interrupts VRS7–VRS0 — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and 4.5.1 PLL Control Register.), controls the hardware center-of-range frequency, fVRS. VRS7–VRS0 cannot be written when the PLLON bit in the PCTL is set. (See 4.3.7 Special Programming Exceptions.
Clock Generator Module (CGM) 4.7.2 Stop Mode If the OSCENINSTOP bit in the CONFIG2 register is cleared (default), then the STOP instruction disables the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the OSCENINSTOP bit in the CONFIG2 register is set, then the phase locked loop is shut off but the oscillator will continue to operate in stop mode. 4.7.
Acquisition/Lock Time Specifications The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRCLK. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections.
Clock Generator Module (CGM) Table 4-5. Example Filter Component Values fRCLK CF1 CF2 RF1 CF 1 MHz 8.2 nF 820 pF 2k 18 nF 2 MHz 4.7 nF 470 pF 2k 6.8 nF 3 MHz 3.3 nF 330 pF 2k 5.6 nF 4 MHz 2.2 nF 220 pF 2k 4.7 nF 5 MHz 1.8 nF 180 pF 2k 3.9 nF 6 MHz 1.5 nF 150 pF 2k 3.3 nF 7 MHz 1.2 nF 120 pF 2k 2.7 nF 8 MHz 1 nF 100 pF 2k 2.2 nF MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev.
Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2.
Configuration Register (CONFIG) Address: $001E Bit 7 Read: 0 Write: Reset: 6 5 4 3 MCLKSEL MCLK1 MCLK0 R 0 0 0 0 R = Reserved 0 = Unimplemented 2 1 Bit 0 TMBCLKSEL OSCENINSTOP SCIBDSRC 0 0 1 Figure 5-1. Configuration Register 2 (CONFIG2) MCLKSEL — MCLK Source Select Bit 1 = Crystal frequency 0 = Bus frequency MCLK1 and MCLK0 — MCLK Output Select Bits Setting the MCLK1 and MCLK0 bits enables the PTD0/SS pin to be used as a MCLK output clock.
Functional Description Address: Read: Write: Reset: $001F Bit 7 6 5 4 3 2 1 Bit 0 COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP COPD 0 0 0 0 See note 0 0 0 Note: LVI5OR3 is only reset via POR (power-on reset). Figure 5-2. Configuration Register 1 (CONFIG1) COPRS — COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS.
Configuration Register (CONFIG) The short stop recovery delay can be enabled when using a crystal or resonator and the OSCENINSTOP bit is set. The short stop recovery delay can be enabled when an external oscillator is used, regardless of the OSCENINSTOP setting. The short stop recovery delay must be disabled when the OSCENINSTOP bit is clear and a crystal or resonator is used. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction.
Chapter 6 Computer Operating Properly (COP) Module 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register. 6.2 Functional Description Figure 6-1 shows the structure of the COP module.
Computer Operating Properly (COP) Module The COP counter is a free-running 6-bit counter preceded by the 12-bit SIM counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 262,128 CGMXCLK cycle overflow option, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms.
COP Control Register 6.3.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Chapter 5 Configuration Register (CONFIG). 6.3.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See Chapter 5 Configuration Register (CONFIG). 6.4 COP Control Register The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector.
Computer Operating Properly (COP) Module To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt when VTST is present on the RST pin.
Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.
Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
CPU Registers 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6.
Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set.
Instruction Set Summary Effect on CCR V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Description Operand Operation Opcode Source Form Address Mode Table
Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X D
Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:
Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 8.2 Features • • • • • • • Features of the IRQ module include: A dedicated external interrupt pin (IRQ) IRQ interrupt control bits Hysteresis buffer Programmable edge-only or edge and level interrupt sensitivity Automatic interrupt acknowledge Internal pullup resistor 8.
External Interrupt (IRQ) RESET ACK TO CPU FOR BIL/BIH INSTRUCTIONS INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF D CLR Q IRQ INTERRUPT REQUEST SYNCHRONIZER CK IRQ IMASK MODE TO MODE SELECT LOGIC HIGH VOLTAGE DETECT Figure 8-1. IRQ Module Block Diagram The vector fetch or software clear may occur before or after the interrupt pin returns to a high level. As long as the pin is low, the interrupt request remains pending.
IRQ Pin 8.4 IRQ Pin A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
External Interrupt (IRQ) 8.6 IRQ Status and Control Register The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin Address: Read: $001D Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 Write: Reset: ACK 0 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 = Unimplemented Figure 8-3.
Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup/pulldown device is also enabled on the pin. 9.
Keyboard Interrupt Module (KBI) INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE VSSAD/VREFL 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2
Functional Description The KBIP7–KBIP0 bits determine the polarity of the keyboard pin detection. These bits along with the MODEK bit determine whether a logic level (0 or 1) and/or a falling (or rising) edge is being detected. • If the keyboard interrupt is edge-sensitive only, a falling (or rising) edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already asserted.
Keyboard Interrupt Module (KBI) If the MODEK bit is set and depending on the KBIPx bit, the keyboard interrupt pins are both falling (or rising) edge and low (or high) level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request.
Low-Power Modes An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction register A. 2. Write 1s (or 0s) to the appropriate port A data register bits. 3.
Keyboard Interrupt Module (KBI) 9.7.1 Keyboard Status and Control Register The keyboard status and control register: • Flags keyboard interrupt requests • Acknowledges keyboard interrupt requests • Masks keyboard interrupt requests • Controls keyboard interrupt triggering sensitivity Address: $001A Read: Bit 7 6 5 4 3 2 0 0 0 0 KEYF 0 Write: Reset: ACKK 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 9-4.
I/O Registers 9.7.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin. Address: $001B Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 Figure 9-5.
Keyboard Interrupt Module (KBI) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev.
Chapter 10 Low-Power Modes 10.1 Introduction The microcontroller (MCU) may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution. This section describes how each module acts in the low-power modes. 10.1.1 Wait Mode The WAIT instruction puts the MCU in a low-power standby mode in which the central processor unit (CPU) clock is disabled but the bus clock continues to run.
Low-Power Modes 10.4 Central Processor Unit (CPU) 10.4.1 Wait Mode The WAIT instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock 10.4.2 Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts.
External Interrupt Module (IRQ) 10.7 External Interrupt Module (IRQ) 10.7.1 Wait Mode The external interrupt (IRQ) module remains active in wait mode. Clearing the IMASK bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of wait mode. 10.7.2 Stop Mode The IRQ module remains active in stop mode. Clearing the IMASK bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of stop mode. 10.
Low-Power Modes 10.11 Serial Peripheral Interface Module (SPI) 10.11.1 Wait Mode The serial peripheral interface (SPI) module remains active in wait mode. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. 10.11.2 Stop Mode The SPI module is inactive in stop mode.
Exiting Wait Mode 10.14 Exiting Wait Mode These events restart the CPU clock and load the program counter with the reset vector or with an interrupt vector: • External reset — A low on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. • External interrupt — A high-to-low transition on an external interrupt pin (IRQ pin) loads the program counter with the contents of locations: $FFFA and $FFFB; IRQ pin.
Low-Power Modes 10.15 Exiting Stop Mode These events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: • External reset — A low on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF.
Chapter 11 Low-Voltage Inhibit (LVI) 11.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF. 11.2 Features Features of the LVI module include: • Programmable LVI reset • Selectable LVI trip voltage • Programmable stop mode operation 11.3 Functional Description Figure 11-1 shows the structure of the LVI module. The LVI is enabled out of reset.
Low-Voltage Inhibit (LVI) LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See Figure 5-2. Configuration Register 1 (CONFIG1) for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 14.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI.
LVI Status Register 11.3.3 Voltage Hysteresis Protection Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS. 11.3.
Low-Voltage Inhibit (LVI) 11.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 11.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 11.6.2 Stop Mode If enabled in stop mode (LVISTOP bit in the configuration register is set), the LVI module remains active in stop mode.
Chapter 12 Input/Output (I/O) Ports 12.1 Introduction Bidirectional input-output (I/O) pins form seven parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, port D and port F are software configurable with pullup devices if configured as input port bits. The pullup devices are automatically and dynamically disabled when a port bit is switched to output mode. 12.
Input/Output (I/O) Ports Addr. $0003 $0004 $0005 $0006 $0007 $0008 $000C $000D $000E $000F Register Name Read: Port D Data Register (PTD) Write: See page 142. Reset: Read: Data Direction Register A (DDRA) Write: See page 136.
Unused Pin Termination Addr. Register Name Port F Data Register Read: (PTF) Write: See page 147. Reset: $0440 Port G Data Register Read: (PTG) Write: See page 149. Reset: $0441 Data Direction Register F Read: (DDRF) Write: See page 148. Reset: $0444 Data Direction Register G Read: (DDRG) Write: See page 150.
Input/Output (I/O) Ports Table 12-1.
Port A 12.3 Port A Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module and the ADC module. Port A also has software configurable pullup devices if configured as an input port. 12.3.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the eight port A pins.
Input/Output (I/O) Ports 12.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer. Address: Read: Write: Reset: $0004 Bit 7 6 5 4 3 2 1 Bit 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 Figure 12-3.
Port A Table 12-2. Port A Pin Functions PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode Accesses to DDRA Accesses to PTA Read/Write Read Write 1 0 X(1) Input, VDD(2) DDRA7–DDRA0 Pin PTA7–PTA0(3) 0 0 X Input, Hi-Z(4) DDRA7–DDRA0 Pin PTA7–PTA0(3) X 1 X Output DDRA7–DDRA0 PTA7–PTA0 PTA7–PTA0 1. X = Don’t care 2. I/O pin pulled up to VDD by internal pullup device 3. Writing affects data register, but does not affect input. 4. Hi-Z = High impedance 12.3.
Input/Output (I/O) Ports 12.4 Port B Port B is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter (ADC) module. 12.4.1 Port B Data Register The port B data register (PTB) contains a data latch for each of the eight port pins. Address: $0001 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 AD7 AD6 AD5 AD2 AD1 AD0 Reset: Unaffected by reset Alternate Function: AD4 AD3 Figure 12-6.
Port B NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 12-8 shows the port B I/O logic. When bit DDRBx is a 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-3 summarizes the operation of the port B pins.
Input/Output (I/O) Ports 12.5 Port C Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. 12.5.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the seven port C pins. NOTE Bit 6 through bit 2 of PTC are not available in the 32-pin LQFP package.
Port C Figure 12-11 shows the port C I/O logic. When bit DDRCx is a 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port C pins.
Input/Output (I/O) Ports 12.5.3 Port C Input Pullup Enable Register The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the seven port C pins. Each bit is individually configurable and requires that the data direction register, DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRC is configured for output mode.
Port D T1CH1 and T1CH0 — Timer 1 Channel I/O Bits The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 17 Timer Interface Module (TIM1) and Chapter 18 Timer Interface Module (TIM2). SPSCK — SPI Serial Clock The PTD3/SPSCK pin is the serial clock input of the SPI module.
Input/Output (I/O) Ports When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-5 summarizes the operation of the port D pins. VDD PTDPUEx READ DDRD ($0007) INTERNAL PULLUP DEVICE WRITE DDRD ($0007) DDRDx INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx READ PTD ($0003) Figure 12-15.
Port E 12.6.3 Port D Input Pullup Enable Register The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each of the eight port D pins. Each bit is individually configurable and requires that the data direction register, DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRD is configured for output mode.
Input/Output (I/O) Ports RxD — SCI Receive Data Input The PTE1/RxD pin is the receive data input for the ESCI module. When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See Chapter 13 Enhanced Serial Communications Interface (ESCI) Module. TxD — SCI Transmit Data Output The PTE0/TxD pin is the transmit data output for the ESCI module.
Port F READ DDRE ($000C) INTERNAL DATA BUS WRITE DDRE ($000C) DDREx RESET WRITE PTE ($0008) PTEx PTEx READ PTE ($0008) Figure 12-19. Port E I/O Circuit Table 12-6. Port E Pin Functions DDRE Bit PTE Bit I/O Pin Mode Accesses to DDRE Read/Write Read Accesses to PTE Write 0 X(1) Input, Hi-Z(2) DDRE5–DDRE0 Pin PTE5–PTE0(3) 1 X Output DDRE5–DDRE0 PTE5–PTE0 PTE5–PTE0 1. X = Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. 12.
Input/Output (I/O) Ports T2CH5–T2CH2 — Timer 2 Channel I/O Bits The PTF7/T2CH5–PTF4/T2CH2 pins are the TIM2 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTF7/T2CH5–PTF4/T2CH2 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 17 Timer Interface Module (TIM1) and Chapter 18 Timer Interface Module (TIM2). 12.8.2 Data Direction Register F Data direction register F (DDRF) determines whether each port F pin is an input or an output.
Port G Table 12-7. Port F Pin Functions DDRF Bit PTF Bit I/O Pin Mode Accesses to DDRF Accesses to PTF Read/Write Read WritE 0 X(1) Input, Hi-Z(2) DDRF7–DDRF0 Pin PTF7–PTF0(3) 1 X Output DDRF7–DDRF0 PTF7–PTF0 PTF7–PTF0 1. X = Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. 12.9 Port G Port G is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter (ADC) module. 12.9.
Input/Output (I/O) Ports 12.9.2 Data Direction Register G Data direction register G (DDRG) determines whether each port G pin is an input or an output. Writing a 1 to a DDRG bit enables the output buffer for the corresponding port G pin; a 0 disables the output buffer. Address: Read: Write: Reset: $0445 Bit 7 6 5 4 3 2 1 Bit 0 DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0 0 0 0 0 0 0 0 0 Figure 12-24.
Chapter 13 Enhanced Serial Communications Interface (ESCI) Module 13.1 Introduction The enhanced serial communications interface (ESCI) module allows asynchronous communications with peripheral devices and other microcontroller units (MCU). 13.
Enhanced Serial Communications Interface (ESCI) Module INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE VSSAD/VREFL 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER SECURITY MODULE MEMORY MAP MODULE PORTF VDDA
Pin Name Conventions 13.3 Pin Name Conventions The generic names of the ESCI input/output (I/O) pins are: • RxD (receive data) • TxD (transmit data) ESCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an ESCI input or output reflects the name of the shared port pin. Table 13-1 shows the full names and the generic names of the ESCI I/O pins. The generic pin names appear in the text of this section. Table 13-1.
Enhanced Serial Communications Interface (ESCI) Module INTERNAL BUS SCI_TxD SCTIE BUS CLOCK R8 TCIE SL T8 SCRIE ILIE TE ACLK BIT IN SCIACTL SCTE RE TxD TRANSMIT SHIFT REGISTER TXINV LINR RxD ARBITER RxD ERROR INTERRUPT CONTROL RECEIVE SHIFT REGISTER ESCI DATA REGISTER RECEIVER INTERRUPT CONTROL TRANSMITTER INTERRUPT CONTROL ESCI DATA REGISTER SBK SCRF OR ORIE IDLE NF NEIE FE FEIE PE SCI_CLK TC RWU PEIE LOOPS LOOPS WAKEUP CONTROL BUS CLOCK CGMXCLK RECEIVE CONTROL ENSCI
Functional Description Addr. $0009 $000A $000B $0013 $0014 $0015 $0016 $0017 $0018 $0019 Register Name Read: ESCI Prescaler Register (SCPSC) Write: See page 175. Reset: Read: ESCI Arbiter Control Register (SCIACTL) Write: See page 179. Reset: Read: ESCI Arbiter Data Register (SCIADAT) Write: See page 180. Reset: Read: ESCI Control Register 1 (SCC1) Write: See page 166. Reset: Read: ESCI Control Register 2 (SCC2) Write: See page 168.
Enhanced Serial Communications Interface (ESCI) Module 13.4.2 Transmitter Figure 13-5 shows the structure of the SCI transmitter and the registers are summarized in Figure 13-4. The baud rate clock source for the ESCI can be selected via the configuration bit, SCIBDSRC.
Functional Description To initiate an ESCI transmission: 1. Enable the ESCI by writing a 1 to the enable ESCI bit (ENSCI) in ESCI control register 1 (SCC1). 2. Enable the transmitter by writing a 1 to the transmitter enable bit (TE) in ESCI control register 2 (SCC2). 3. Clear the ESCI transmitter empty bit (SCTE) by first reading ESCI status register 1 (SCS1) and then writing to the SCDR. For 9-bit data, also write the T8 bit in SCC3. 4. Repeat step 3 for each subsequent transmission.
Enhanced Serial Communications Interface (ESCI) Module 13.4.2.4 Idle Characters For TXINV = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress.
Functional Description INTERNAL BUS SCP1 SCR1 SCP0 SCR0 DATA RECOVERY PDS2 ALL ZEROS RPF PDS1 PDS0 PSSB4 PSSB3 PSSB2 11-BIT RECEIVE SHIFT REGISTER STOP ÷ 16 RxD BKF CGMXCLK OR BUS CLOCK BAUD DIVIDER H ALL ONES PRESCALER PRESCALER ÷4 ESCI DATA REGISTER 8 7 6 M WAKE ILTY PSSB1 PEN PSSB0 PTY PARITY CHECKING SCRF SCRIE OR ORIE NF NEIE ERROR CPU INTERRUPT REQUEST 5 4 3 2 SCRF WAKEUP LOGIC IDLE ILIE CPU INTERRUPT REQUEST START SCR2 1 0 L MSB LINR FE FEIE PE PEIE RWU
Enhanced Serial Communications Interface (ESCI) Module 13.4.3.2 Character Reception During an ESCI reception, the receive shift register shifts characters in from the RxD pin. The ESCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR.
Functional Description If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-3 summarizes the results of the data bit samples. Table 13-3.
Enhanced Serial Communications Interface (ESCI) Module actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character.
Functional Description STOP IDLE OR NEXT CHARACTER RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK DATA SAMPLES Figure 13-9. Fast Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
Enhanced Serial Communications Interface (ESCI) Module NOTE With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle will cause the receiver to wake up. 13.4.3.7 Receiver Interrupts These sources can generate CPU interrupt requests from the ESCI receiver: • ESCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request.
ESCI During Break Module Interrupts 13.6 ESCI During Break Module Interrupts The BCFE bit in the break flag control register (SBFCR) enables software to clear status bits during the break state. See 19.2 Break Module (BRK). To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to the BCFE bit.
Enhanced Serial Communications Interface (ESCI) Module 13.8.1 ESCI Control Register 1 ESCI control register 1 (SCC1): • Enables loop mode operation • Enables the ESCI • Controls output polarity • Controls character length • Controls ESCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type Address: $0013 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 Figure 13-10.
I/O Registers Table 13-5.
Enhanced Serial Communications Interface (ESCI) Module • • • • Enables the transmitter Enables the receiver Enables ESCI wakeup Transmits ESCI break characters Address: $0014 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 13-11. ESCI Control Register 2 (SCC2) SCTIE — ESCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate ESCI transmitter CPU interrupt requests.
I/O Registers RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE Writing to the RE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1. RWU — Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
Enhanced Serial Communications Interface (ESCI) Module When the ESCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 — Transmitted Bit 8 When the ESCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset clears the T8 bit.
I/O Registers SCTE — ESCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an ESCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an ESCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
Enhanced Serial Communications Interface (ESCI) Module BYTE 1 BYTE 2 BYTE 3 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 NORMAL FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1 READ SCDR BYTE 2 READ SCDR BYTE 3 BYTE 1 BYTE 2 BYTE 3 SCRF = 0 OR = 0 SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 DELAYED FLAG CLEARING SEQUENCE BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCS1 SCRF = 1 OR = 1 RE
I/O Registers 13.8.5 ESCI Status Register 2 ESCI status register 2 (SCS2) contains flags to signal these conditions: • Break character detected • Incoming data Address: Read: $0017 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 BKF RPF 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 13-15. ESCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the ESCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set.
Enhanced Serial Communications Interface (ESCI) Module 13.8.7 ESCI Baud Rate Register The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for both the receiver and the transmitter. NOTE There are two prescalers available to adjust the baud rate. One in the ESCI baud rate register and one in the ESCI prescaler register.
I/O Registers SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits These read/write bits select the baud rate register prescaler divisor as shown in Table 13-7. Reset clears SCP1 and SCP0. Table 13-7. ESCI Baud Rate Prescaling SCP[1:0] Baud Rate Register Prescaler Divisor (BPD) 0 0 1 0 1 3 1 0 4 1 1 13 SCR2–SCR0 — ESCI Baud Rate Select Bits These read/write bits select the ESCI baud rate divisor as shown in Table 13-8. Reset clears SCR2–SCR0. Table 13-8.
Enhanced Serial Communications Interface (ESCI) Module PDS2–PDS0 — Prescaler Divisor Select Bits These read/write bits select the prescaler divisor as shown in Table 13-9. Reset clears PDS2–PDS0. NOTE The setting of ‘000’ will bypass this prescaler. It is not recommended to bypass the prescaler while ENSCI is set, because the switching is not glitch free. Table 13-9.
ESCI Arbiter Table 13-10. ESCI Prescaler Divisor Fine Adjust (Continued) PSSB[4:3:2:1:0] Prescaler Divisor Fine Adjust (PDFA) 1 0 0 0 0 16/32 = 0.5 1 0 0 0 1 17/32 = 0.53125 1 0 0 1 0 18/32 = 0.5625 1 0 0 1 1 19/32 = 0.59375 1 0 1 0 0 20/32 = 0.625 1 0 1 0 1 21/32 = 0.65625 1 0 1 1 0 22/32 = 0.6875 1 0 1 1 1 23/32 = 0.71875 1 1 0 0 0 24/32 = 0.75 1 1 0 0 1 25/32 = 0.78125 1 1 0 1 0 26/32 = 0.8125 1 1 0 1 1 27/32 = 0.84375 1 1 1 0 0 28/32 = 0.875 1 1 1 0 1 29/32 = 0.
Enhanced Serial Communications Interface (ESCI) Module Table 13-11. ESCI Baud Rate Selection Examples PDS[2:1:0] PSSB[4:3:2:1:0] SCP[1:0] Prescaler Divisor (BPD) SCR[2:1:0] Baud Rate Divisor (BD) 0 0 0 X X X X X 0 0 1 0 0 0 1 76,800 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 9600 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 9562.65 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 9525.58 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 8563.
ESCI Arbiter 13.9.1 ESCI Arbiter Control Register Address: $000A Bit 7 Read: Write: Reset: AM1 0 6 ALOST 0 5 4 AM0 ACLK 0 0 3 2 1 Bit 0 AFIN ARUN AROVFL ARD8 0 0 0 0 = Unimplemented Figure 13-19. ESCI Arbiter Control Register (SCIACTL) AM1 and AM0 — Arbiter Mode Select Bits These read/write bits select the mode of the arbiter module as shown in Table 13-12. Reset clears AM1 and AM0. Table 13-12.
Enhanced Serial Communications Interface (ESCI) Module AROVFL— Arbiter Counter Overflow Bit This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to SCIACTL. Writing 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears AROVFL. 1 = Arbiter counter overflow has occurred 0 = No arbiter counter overflow has occurred ARD8— Arbiter Counter MSB This read-only bit is the MSB of the 9-bit arbiter counter. Clear ARD8 by writing any value to SCIACTL.
ESCI Arbiter If SCI_TxD senses 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration operation will be restarted after the next rising edge of SCI_TxD. MEASURED TIME CPU READS RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 COUNTER STARTS, ARUN = 1 CPU WRITES SCIACTL WITH $20 RXD Figure 13-21. Bit Time Measurement with ACLK = 0 MEASURED TIME CPU READS RESULT OUT OF SCIADAT CPU WRITES SCIACTL WITH $30 COUNTER STARTS, ARUN = 1 COUNTER STOPS, AFIN = 1 RXD Figure 13-22.
Enhanced Serial Communications Interface (ESCI) Module MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev.
Chapter 14 System Integration Module (SIM) 14.1 Introduction This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 14-1. Table 14-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing.
System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM) SIM COUNTER CGMXCLK (FROM CGM) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL VDD CLOCK GENERATORS INTERNAL PULLUP DEVICE RESET PIN LOGIC INTERNAL CLOCKS FORCED MONITOR MODE ENTRY LVI (FROM LVI MODULE) POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET
Introduction 7 Addr. Register Name $FE00 Read: Break Status Register (BSR) Write: See page 199. Reset: Bit 7 6 5 4 3 2 1 R R R R R R 0 0 0 0 0 0 0 0 SBSW Note(1) Bit 0 R 1. Writing a 0 clears SBSW. $FE01 $FE03 $FE04 $FE05 $FE06 $FE07 Read: SIM Reset Status Register (SRSR) Write: See page 199. POR: Read: Break Flag Control Register (BFCR) Write: See page 200.
System Integration Module (SIM) 14.2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 14-3. This clock originates from either an external oscillator or from the on-chip PLL. 14.2.1 Bus Timing In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four.
Reset and System Initialization 14.3 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • Illegal address • Forced monitor mode entry reset (MODRST) All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the internal reset signal (IRST).
System Integration Module (SIM) RST PULLED LOW BY MCU RST 32 CYCLES 32 CYCLES CGMXCLK IAB VECTOR HIGH Figure 14-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR MODRST INTERNAL RESET Figure 14-6. Sources of Internal Reset Table 14-2. Reset Recovery Reset Recovery Type Actual Number of Cycles POR/LVI 4163 (4096 + 64 + 3) All others 67 (64 + 3) 14.3.2.
Reset and System Initialization OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES CGMXCLK CGMOUT RST $FFFE IAB $FFFF Figure 14-7. POR Recovery 14.3.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the CONFIG1 register is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset.
System Integration Module (SIM) 14.4 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus clocks. The SIM counter also serves as a prescaler for the computer operating properly (COP) module. The SIM counter overflow supplies the clock for the COP module. The SIM counter is 12 bits long. 14.4.
Exception Control 14.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts.
System Integration Module (SIM) FROM RESET BREAK INTERRUPT ? NO YES YES BITSET? SET? IIBIT NO IRQ INTERRUPT ? NO YES CGM INTERRUPT ? NO YES OTHER INTERRUPTS ? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION ? YES NO RTI INSTRUCTION ? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 14-10. Interrupt Processing MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev.
Exception Control If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 14-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
System Integration Module (SIM) Table 14-3.
Exception Control Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 14-12. Interrupt Status Register 1 (INT1) IF6–IF1 — Interrupt Flags 1–6 These flags indicate the presence of interrupt requests from the sources shown in Table 14-3.
System Integration Module (SIM) Interrupt Status Register 4 Address: $FE07 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 IF24 IF23 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 14-15. Interrupt Status Register 4 (INT4) Bits 7–2 — Always read 0 IF24–IF23 — Interrupt Flags 24–23 These flags indicate the presence of an interrupt request from the source shown in Table 14-3. 1 = Interrupt request present 0 = No interrupt request present 14.5.
Low-Power Modes 14.6.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 14-16 shows the timing for wait mode entry. A module that is active during wait mode can wakeup the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive.
System Integration Module (SIM) 14.6.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset also causes an exit from stop mode. The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in CONFIG1.
SIM Registers 14.7 SIM Registers The SIM has three memory-mapped registers. Table 14-4 shows the mapping of these registers. Table 14-4. SIM Registers Address Register Access Mode $FE00 BSR User $FE01 SRSR User $FE03 BFCR User 14.7.1 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode.
System Integration Module (SIM) POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch f
Chapter 15 Serial Peripheral Interface (SPI) Module 15.1 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. 15.
Serial Peripheral Interface (SPI) Module INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE VSSAD/VREFL 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD
Functional Description INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER BUSCLK 7 6 5 4 3 2 1 MISO 0 ÷2 MOSI ÷8 CLOCK DIVIDER RECEIVE DATA REGISTER ÷ 32 PIN CONTROL LOGIC ÷ 128 SPMSTR SPE CLOCK SELECT SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR CPHA MODFEN TRANSMITTER CPU INTERRUPT REQUEST CPOL SPWOM ERRIE SPI CONTROL SPTIE RECEIVER/ERROR CPU INTERRUPT REQUEST SPRIE SPE SPRF SPTE OVRF MODF Figure 15-2. SPI Module Block Diagram Addr.
Serial Peripheral Interface (SPI) Module 15.3.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE In a multi-SPI system, configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See 15.12.1 SPI Control Register. Only a master SPI module can initiate transmissions.
Transmission Formats an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin.
Serial Peripheral Interface (SPI) Module general-purpose I/O not affecting the SPI. (See 15.6.2 Mode Fault Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave’s SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 15-6.
Transmission Formats edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line.
Serial Peripheral Interface (SPI) Module WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 5 BIT 6 SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 1 3 2 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST BUS CLOCK WRITE TO SPDR EARLIEST BUS CLOCK WRITE TO SPDR EARLIEST BUS CLOCK WRITE TO SPDR EARLIEST LATEST SPSCK = BUS CLOCK ÷ 2; 2 POSSIBLE START POINTS SPSCK = BUS CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK ÷ 32; 32 POSSIBLE ST
Queuing Transmission Data 15.5 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when SPTE is high.
Serial Peripheral Interface (SPI) Module 15.6 Error Conditions The following flags signal SPI error conditions: • Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register.
Error Conditions BYTE 1 BYTE 2 BYTE 3 BYTE 4 1 4 6 8 SPRF OVRF READ SPSCR 2 5 READ SPDR 3 7 1 BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT. 3 4 5 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 6 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 7 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. 8 BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
Serial Peripheral Interface (SPI) Module 15.6.2 Mode Fault Error Setting SPMSTR selects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR.
Interrupts In a slave SPI (MSTR = 0), MODF generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by clearing the SPE bit of the slave. NOTE A high on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission.
Serial Peripheral Interface (SPI) Module The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error CPU interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.
SPI During Break Interrupts 15.9.2 Stop Mode The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. 15.10 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state.
Serial Peripheral Interface (SPI) Module When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port. 15.11.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
I/O Registers Table 15-2. SPI Configuration SPE SPMSTR MODFEN SPI Configuration Function of SS Pin 0 X(1)) X Not enabled General-purpose I/O; SS ignored by SPI 1 0 X Slave Input-only to SPI 1 1 0 Master without MODF General-purpose I/O; SS ignored by SPI 1 1 1 Master with MODF Input-only to SPI 1. X = Don’t care 15.
Serial Peripheral Interface (SPI) Module CPOL — Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 15-5 and Figure 15-7.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears the CPOL bit. CPHA — Clock Phase Bit This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 15-5 and Figure 15-7.
I/O Registers SPRF — SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Reset clears the SPRF bit.
Serial Peripheral Interface (SPI) Module If the MODFEN bit is 0, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. See 15.6.2 Mode Fault Error. SPR1 and SPR0 — SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in Table 15-3.
Chapter 16 Timebase Module (TBM) 16.1 Introduction This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the external clock source. This TBM version uses 15 divider stages, eight of which are user selectable. A configuration option bit to select an additional 128 divide of the external clock source can be selected. See Chapter 5 Configuration Register (CONFIG) 16.
Timebase Module (TBM) TMBCLKSEL FROM CONFIG2 CGMXCLK FROM CGM MODULE TBMCLK 0 1 DIVIDE BY 128 PRESCALER TBON ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 TACK ÷2 TBR0 ÷2 TBR1 ÷2 TBR2 TBMINT TBIF 000 TBIE R 001 010 100 SEL 011 101 110 111 Figure 16-1. Timebase Block Diagram 16.
Low-Power Modes Table 16-1. Timebase Divider Selection Divider TBR2 TBR1 TBR0 0 0 0 0 0 TMBCLKSEL 0 1 0 32,768 4,194,304 1 8192 1,048,576 1 0 2048 262144 0 1 1 128 16,384 1 0 0 64 8192 1 0 1 32 4096 1 1 0 16 2048 1 1 1 8 1024 As an example, a 4.9152 MHz crystal, with the TMBCLKSEL set for divide-by-128 and the TBR2–TBR0 set to {011}, the divider is 16,384 and the interrupt rate calculates to: 16,384 4.9152 x 106 = 3.
Timebase Module (TBM) 16.7 Timebase Control Register The timebase has one register, the timebase control register (TBCR), which is used to enable the timebase interrupts and set the rate. Address: $001C Bit 7 Read: TBIF Write: Reset: 0 6 5 4 TBR2 TBR1 TBR0 0 0 0 = Unimplemented 3 2 1 Bit 0 TBIE TBON R 0 0 0 0 R = Reserved 0 TACK Figure 16-2. Timebase Control Register (TBCR) TBIF — Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over.
Chapter 17 Timer Interface Module (TIM1) 17.1 Introduction This section describes the timer interface module (TIM1). TIM1 is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 17-2 is a block diagram of the TIM1. 17.
Timer Interface Module (TIM1) INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE VSSAD/VREFL 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2)
Functional Description PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF INTERRUPT LOGIC TOIE 16-BIT COMPARATOR T1MODH:T1MODL TOV0 CHANNEL 0 ELS0B ELS0A PORT LOGIC CH0MAX 16-BIT COMPARATOR T1CH0H:T1CH0L PTD4/T1CH0 CH0F INTERRUPT LOGIC 16-BIT LATCH CH0IE MS0A MS0B INTERNAL BUS TOV1 CHANNEL 1 ELS1B ELS1A PORT LOGIC CH1MAX 16-BIT COMPARATOR T1CH1H:T1CH1L PTD5/T1CH1 CH1F INTERRUPT LOGIC 16-BIT LATCH CH1IE MS1A Figure 17-2.
Timer Interface Module (TIM1) Addr. $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A Register Name TIM1 Counter Modulo Register High (T1MODH) See page 236. TIM1 Counter Modulo Register Low (T1MODL) See page 236. TIM1 Channel 0 Status and Control Register (T1SC0) See page 237. TIM1 Channel 0 Register High (T1CH0H) See page 240. TIM1 Channel 0 Register Low (T1CH0L) See page 240. TIM1 Channel 1 Status and Control Register (T1SC1) See page 237. TIM1 Channel 1 Register High (T1CH1H) See page 240.
Functional Description 17.3.3 Output Compare With the output compare function, the TIM1 can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM1 can set, clear, or toggle the channel pin. Output compares can generate TIM1 CPU interrupt requests. 17.3.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 17.3.3 Output Compare.
Timer Interface Module (TIM1) 17.3.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM1 can generate a PWM signal. The value in the TIM1 counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM1 counter modulo registers. The time between overflows is the period of the PWM signal.
Functional Description Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value.
Timer Interface Module (TIM1) 4. In TIM1 channel x status and control register (T1SCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 17-2. b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on compare) to the edge/level select bits, ELSxB:ELSxA.
TIM1 During Break Interrupts If TIM1 functions are not required during wait mode, reduce power consumption by stopping the TIM1 before executing the WAIT instruction. 17.6 TIM1 During Break Interrupts A break interrupt stops the TIM1 counter and inhibits input captures. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state.
Timer Interface Module (TIM1) Address: $0020 Bit 7 Read: TOF Write: 0 Reset: 0 6 5 TOIE TSTOP 0 1 4 3 0 0 TRST 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 = Unimplemented Figure 17-5. TIM1 Status and Control Register (T1SC) TOF — TIM1 Overflow Flag Bit This read/write flag is set when the TIM1 counter reaches the modulo value programmed in the TIM1 counter modulo registers. Clear TOF by reading the TIM1 status and control register when TOF is set and then writing a 0 to TOF.
Input/Output Registers PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM1 counter as Table 17-1 shows. Reset clears the PS[2:0] bits. Table 17-1.
Timer Interface Module (TIM1) 17.8.3 TIM1 Counter Modulo Registers The read/write TIM1 modulo registers contain the modulo value for the TIM1 counter. When the TIM1 counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM1 counter resumes counting from $0000 at the next timer clock. Writing to the high byte (T1MODH) inhibits the TOF bit and overflow interrupts until the low byte (T1MODL) is written. Reset sets the TIM1 counter modulo registers.
Input/Output Registers Address: $0025 Bit 7 T1SC0 6 5 4 3 2 1 Bit 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 5 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 Read: CH0F Write: 0 Reset: 0 0 Address: $0028 T1SC1 Bit 7 Read: CH1F Write: 0 Reset: 0 6 CH1IE 0 0 0 = Unimplemented Figure 17-8.
Timer Interface Module (TIM1) When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Table 17-2). Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM1 status and control register (T1SC).
Input/Output Registers NOTE When TOVx is set, a TIM1 counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 17-9 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
Timer Interface Module (TIM1) Address: $0026 Read: Write: T1CH0H Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after reset Address: $0027 Read: Write: T1CH0L Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: Indeterminate after reset Address: $0029 Read: Write: T1CH1H Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate aft
Chapter 18 Timer Interface Module (TIM2) 18.1 Introduction This section describes the timer interface module (TIM2). The TIM2 is a 6-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 18-2 is a block diagram of the TIM2. 18.
Timer Interface Module (TIM2) INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE VSSAD/VREFL 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2)
Functional Description TCLK PTD6/T2CH0 INTERNAL BUS CLOCK PRESCALER SELECT PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR T2MODH:T2MODL CHANNEL 0 ELS0B ELS0A TOV0 CH0MAX 16-BIT COMPARATOR T2CH0H:T2CH0L CH0F 16-BIT LATCH MS0A CHANNEL 1 ELS1B ELS1A TOV1 CH1MAX 16-BIT COMPARATOR T2CH1H:T2CH1L CH0IE MS0B CH1F 16-BIT LATCH CH1IE MS1A CHANNEL 2 ELS2B ELS2A TOV2 CH2MAX 16-BIT COMPARATOR T2CH2H:T2CH2L CH2F 16-BIT LATCH MS2A CHANNEL 3 ELS
Timer Interface Module (TIM2) Addr. Register Name Bit 7 TOF $002B TIM2 Status and Control Read: Register (T2SC) Write: See page 252. Reset: $002C $002D 1 Bit 0 PS2 PS1 PS0 1 0 0 0 0 0 TIM2 Counter Register High Read: (T2CNTH) Write: See page 254. Reset: Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 TIM2 Counter Register Low Read: (T2CNTL) Write: See page 254.
Functional Description Addr. $0457 $0458 $0459 Register Name TIM2 Channel 2 Register High Read: (T2CH2H) Write: See page 258. Reset: TIM2 Channel 2 Register Low Read: (T2CH2L) Write: See page 258. Reset: TIM2 Channel 3 Status and Read: Control Register (T2SC3) Write: See page 255. Reset: $045A TIM2 Channel 3 Register High Read: (T2CH3H) Write: See page 258. Reset: $045B TIM2 Channel 3 Register Low Read: (T2CH3L) Write: See page 258.
Timer Interface Module (TIM2) 18.3.2 Input Capture An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The polarity of the active edge is programmable.
Functional Description compare value may cause the compare to be missed. The TIM2 may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: • When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse.
Timer Interface Module (TIM2) channel. Writing to the active channel registers is the same as generating unbuffered output compares. 18.3.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM2 can generate a PWM signal. The value in the TIM2 counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM2 counter modulo registers.
Functional Description Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value.
Timer Interface Module (TIM2) NOTE In buffered PWM signal generation, do not write pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 18.3.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1.
Interrupts Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 18.8.4 TIM2 Channel Status and Control Registers.) 18.4 Interrupts The following TIM2 sources can generate interrupt requests: • TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter reaches the modulo value programmed in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable bit, TOIE, enables TIM2 overflow interrupt requests.
Timer Interface Module (TIM2) 18.7 I/O Signals Port D shares two of its pins with the TIM2. Port F shares four of its pins with the TIM2. PTD6/T2CH0 is an external clock input to the TIM2 prescaler. The six TIM2 channel I/O pins are PTD6/T2CH0, PTD7/T2CH1, PTF4/T2CH2, PTF5/T2CH3, PTF6/T2CH4, and PTF7/T2CH5. 18.7.1 TIM2 Clock Pin (T2CH0) T2CH0 is an external clock input that can be the clock source for the TIM2 counter instead of the prescaled internal bus clock.
I/O Registers TOF — TIM2 Overflow Flag Bit This read/write flag is set when the TIM2 counter resets reaches the modulo value programmed in the TIM2 counter modulo registers. Clear TOF by reading the TIM2 status and control register when TOF is set and then writing a 0 to TOF. If another TIM2 overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit.
Timer Interface Module (TIM2) 18.8.2 TIM2 Counter Registers The two read-only TIM2 counter registers contain the high and low bytes of the value in the TIM2 counter. Reading the high byte (T2CNTH) latches the contents of the low byte (T2CNTL) into a buffer. Subsequent reads of T2CNTH do not affect the latched T2CNTL value until T2CNTL is read. Reset clears the TIM2 counter registers. Setting the TIM2 reset bit (TRST) also clears the TIM2 counter registers.
I/O Registers 18.8.
Timer Interface Module (TIM2) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM2 counter registers matches the value in the TIM2 channel x registers. When CHxIE = 1, clear CHxF by reading TIM2 channel x status and control register with CHxF set, and then writing a 0 to CHxF.
I/O Registers Table 18-2.
Timer Interface Module (TIM2) CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at a 1 and clear output on compare is selected, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 18-9 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at 100% duty cycle level until the cycle after CHxMAX is cleared.
I/O Registers Address: $0034 Read: Write: T2CH1H Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after reset Address: $0035 Read: Write: T2CH1L Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: Indeterminate after reset Address: $0457 Read: Write: T2CH2H Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after reset Addres
Timer Interface Module (TIM2) Address: $0460 Read: Write: T2CH5H Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after reset Address: $0461 Read: Write: Reset: T2CH5L Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indeterminate after reset Figure 18-10. TIM2 Channel Registers (T2CH0H/L:T2CH5H/L) (Sheet 3 of 3) MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev.
Chapter 19 Development Support 19.1 Introduction This section describes the break module, the monitor module (MON), and the monitor mode entry methods. 19.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
Development Support INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE VSSAD/VREFL 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2
Break Module (BRK) ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] BKPT (TO SIM) CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] Figure 19-2. Break Module Block Diagram Addr. Register Name $FE00 Read: Break Status Register (BSR) Write: See page 266. Reset: $FE03 $FE09 $FE0A $FE0B Read: Break Flag Control Register (BFCR) Write: See page 266. Reset: Read: Break Address High Register (BRKH) Write: See page 265.
Development Support When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not execute
Break Module (BRK) 19.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: $FE0B Read: Write: Reset: Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 19-4. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit.
Development Support 19.2.2.3 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Address: $FE00 Bit 7 Read: Write: R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note(1) Reset: Bit 0 R 0 R = Reserved 1. Writing a 0 clears SBSW. Figure 19-7. Break Status Register (BSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine.
Monitor Module (MON) 19.3 Monitor Module (MON) The monitor module allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
Development Support POR RESET NO CONDITIONS FROM Table 19-1 PTA0 = 1, PTA1 = 0, RESET VECTOR BLANK? IRQ = VTST? YES PTA0 = 1, PTA1 = 0, PTB0 = 1, AND PTB1 = 0? NO NO YES YES FORCED MONITOR MODE NORMAL USER MODE NORMAL MONITOR MODE INVALID USER MODE HOST SENDS 8 SECURITY BYTES IS RESET POR? YES NO YES ARE ALL SECURITY BYTES CORRECT? ENABLE FLASH NO DISABLE FLASH MONITOR MODE ENTRY DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) EXECUTE MONITOR CODE YES DOES RESET OCCUR? NO
Monitor Module (MON) MC68HC908GR60A N.C. VDD RST 27 pF 1 1 μF + 3 4 1 μF + VDD VCC 16 C1+ C1– GND 15 C2+ V+ 2 + DB9 3 7 10 8 9 0.1 μF VDD OSC1 8 MHz + 10 k 1 μF PTB4 1 kΩ VDD + 2 1 μF VDDAD 10 MΩ 27 pF V– 6 5 C2– VDDA OSC2 MAX232 1 μF PTB0 IRQ 10 k 10 k 9.1 V PTB1 10 k PTA1 10 kΩ 74HC125 5 6 74HC125 3 2 VDD VSSAD PTA0 VSSA VSS 4 1 5 Figure 19-10. Normal Monitor Mode Circuit MC68HC908GR60A N.C.
Development Support Table 19-1. Monitor Mode Signal Requirements and Options Mode IRQ RST Reset Vector Serial Communication Mode Selection Communication Speed Divider PLL PTA0 PTA1 PTB0 PTB1 PTB4 COP External Bus Clock Frequency Baud Rate VTST VDD or VTST X 1 0 1 0 0 OFF Disabled 4.0 MHz 2.0 MHz 7200 VTST VDD or VTST X 1 0 1 0 1 OFF Disabled 8.0 MHz 2.0 MHz 7200 Forced Monitor VDD or VSS VDD $FF (blank) 1 0 X X X OFF Disabled 8.0 MHz 2.
Monitor Module (MON) 19.3.1.1 Normal Monitor Mode If VTST is applied to IRQ and PTB4 is low upon monitor mode entry, the bus frequency is a divide-by-two of the input clock. If PTB4 is high with VTST applied to IRQ upon monitor mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTB4 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied to IRQ.
Development Support 19.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT Figure 19-12. Monitor Data Format 19.3.1.5 Break Signal A start bit (0) followed by nine 0 bits is a break signal.
Monitor Module (MON) FROM HOST 4 ADDRESS HIGH READ READ 4 1 ADDRESS HIGH ADDRESS LOW 1 ADDRESS LOW 4 DATA 1 3, 2 4 ECHO RETURN Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Figure 19-14.
Development Support Table 19-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE ADDRESS HIGH WRITE ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 19-5.
Monitor Module (MON) Table 19-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 19-8.
Development Support 19.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
Chapter 20 Electrical Specifications 20.1 Introduction This section contains electrical and timing specifications. 20.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 20.5 5.0-Vdc Electrical Characteristics for guaranteed operating conditions. Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to + 6.
Electrical Specifications 20.3 Functional Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit TA –40 to +125 °C VDD 5.0 ±10% 3.3 ±10% V 20.
5.0-Vdc Electrical Characteristics 20.5 5.0-Vdc Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.8 VDD – 1.5 VDD – 1.5 — — — — — — — — 50 V V V mA IOH2 — — 50 mA IOHT — — 100 mA VOL VOL VOL IOL1 — — — — — — — — 0.4 1.5 1.5 50 V V V mA IOL2 — — 50 mA IOLT — — 100 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.
Electrical Specifications Characteristic(1) Symbol Min Typ(2) Max Unit Pullup/pulldown resistors (as input only) Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0/CANTX, PTD7/T2CH1–PTD0/SS RPU 20 45 65 kΩ Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD + 2.5 — VDD + 4.0 V Low-voltage inhibit, trip falling voltage VTRIPF 3.90 4.25 4.50 V Low-voltage inhibit, trip rising voltage VTRIPR 4.0 4.35 4.
3.3-Vdc Electrical Characteristics 20.6 3.3-Vdc Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.3 VDD – 1.0 VDD – 1.0 — — — — — — — — 30 V V V mA IOH2 — — 30 mA IOHT — — 60 mA VOL VOL VOL IOL1 — — — — — — — — 0.3 1.0 0.8 30 V V V mA IOL2 — — 30 mA IOLT — — 60 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.
Electrical Specifications Characteristic(1) Symbol Min Typ(2) Max Unit Pullup/pulldown resistors (as input only) Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0, PTD7/T2CH1–PTD0/SS RPU 20 45 65 kΩ Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD + 2.5 — VDD + 4.0 V Low-voltage inhibit, trip falling voltage VTRIPF 2.35 2.6 2.8 V Low-voltage inhibit, trip rising voltage VTRIPR 2.4 2.66 2.
5.0-Volt Control Timing 20.7 5.0-Volt Control Timing Characteristic(1) Symbol Min Max Unit fOSC 1 dc 8 32 MHz Internal operating frequency fOP (fBus) — 8 MHz Internal clock period (1/fOP) tCYC 125 — ns RESET input pulse width low tRL 100 — ns IRQ interrupt pulse width low (edge-triggered) tILIH 100 — ns tILIL Note 3 — tCYC Frequency of operation Crystal option External clock option(2) (3) IRQ interrupt pulse period 1.
Electrical Specifications 20.9 Clock Generation Module (CGM) Characteristics 20.9.1 CGM Operating Conditions Characteristic Symbol Min Typ Max Unit Operating voltage VDDA VSSA VDD – 0.3 VSS – 0.3 — — VDD + 0.3 VSS + 0.3 V Crystal reference frequency fRCLK 1 — 8 MHz Input clock frequency (PLL off)(1) fXCLK — — 32 MHz Range nominal multiplier fNOM — 71.42 — kHz VCO center-of-range frequency(2) fVRS 71.42k — 40M Hz VCO operating frequency(3) fVCLK 71.42k — 32M Hz 1.
Clock Generation Module (CGM) Characteristics 20.9.3 CGM Acquisition/Lock Time Information Characteristic Symbol Min Typ Max Unit Acquisition mode entry frequency tolerance(1) ΔACQ ± 3.6 — ± 7.2 % Tracking mode entry frequency tolerance(2) ΔTRK 0 — ± 3.6 % LOCK entry frequency tolerance(3) ΔLOCK 0 — ± 0.9 % LOCK exit frequency tolerance(4) ΔUNL ± 0.9 — ± 1.
Electrical Specifications 20.10 5.0-Volt ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 4.5 5.5 V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VDDAD Resolution BAD 10 10 Bits Absolute accuracy AAD –4 +4 LSB Includes quantization ADC internal clock fADIC 500 k 1.
3.3-Volt ADC Characteristics 20.11 3.3-Volt ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 3.0 3.6 V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VDDAD Resolution BAD 10 10 Bits Absolute accuracy AAD –6 +6 LSB Includes quantization ADC internal clock fADIC 500 k 1.
Electrical Specifications 20.12 5.
3.3-Volt SPI Characteristics 20.13 3.
Electrical Specifications SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT MSB IN BITS 6–1 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
3.
Electrical Specifications 20.14 Timer Interface Module Characteristics Characteristic Symbol Min Max Unit tTH, tTL 2 — tcyc tTLTL Note(1) — tcyc tTCL, tTCH tcyc + 5 — ns Timer input capture pulse width Timer input capture period Timer input clock pulse width 1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
Memory Characteristics 20.15 Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz fRead(1) 0 — 8M Hz FLASH page erase time <1 k cycles >1 k cycles tErase 0.9 3.6 1 4 1.1 5.
Electrical Specifications MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev.
Chapter 21 Ordering Information and Mechanical Specifications 21.1 Introduction This section contains ordering numbers for the MC68HC908GR60A and gives the dimensions for: • 32-pin low-profile quad flat pack (case 873A) • 48-pin low-profile quad flat pack (case 932-03) • 64-pin quad flat pack (case 840B) The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Semiconductor Sales Office.
Appendix A MC68HC908GR48A A.1 Introduction The MC68HC908GR48A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. The information contained in this document pertains to the MC68HC908GR48A with the exceptions shown in this appendix. A.2 Block Diagram See Figure A-1. A.
INTERNAL BUS MONITOR ROM — 304 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE VSSAD/VREFL 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/M
$0000 ↓ $003F I/O REGISTERS 64 BYTES $0040 ↓ $043F RAM-1 1024 BYTES $0440 ↓ $0461 I/O REGISTERS 34 BYTES $0462 ↓ $057F RESERVED $0580 ↓ $077F RAM-2 512 BYTES $0780 ↓ $1DFF RESERVED $1E00 ↓ $1E0F MONITOR ROM 16 BYTES $1E10 ↓ $3FFF RESERVED $4000 ↓ $7FFF FLASH-2 16,384 BYTES $8000 ↓ $FDFF FLASH-1 32,256 BYTES $FE00 SIM BREAK STATUS REGISTER (BSR) $FE01 SIM RESET STATUS REGISTER (SRSR) $FE02 RESERVED $FE03 SIM BREAK FLAG CONTROL REGISTER (BFCR) $FE04 INTERRUPT STATUS REGISTER 1 (IN
A.4 Ordering Information Table A-1.
Appendix B MC68HC908GR32A B.1 Introduction The MC68HC908GR32A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. The information contained in this document pertains to the MC68HC908GR32A with the exceptions shown in this appendix. B.2 Block Diagram See Figure B-1. B.
INTERNAL BUS MONITOR ROM — 304 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE VSSAD/VREFL 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER SECURITY MODULE MEMORY MAP MODULE PORTF VDDAD/VREFH PTE5–PTE2 PTE1/RxD PTE0/TxD PTF7/T
$0000 ↓ $003F I/O REGISTERS 64 BYTES $0040 ↓ $043F RAM-1 1024 BYTES $0440 ↓ $0461 I/O REGISTERS 34 BYTES $FE04 INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 INTERRUPT STATUS REGISTER 4 (INT4) $FE08 UNIMPLEMENTED $FE09 BREAK ADDRESS REGISTER HIGH (BRKH) $FE0A BREAK ADDRESS REGISTER LOW (BRKL) $FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR) $FE0C LVI STATUS REGISTER (LVISR) $FE0D UNIMPLEMENTED $FE0E FLASH-
B.4 Ordering Information Table B-1.
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