Datasheet

MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor 109
Chapter 8
External Interrupt (IRQ)
8.1 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
8.2 Features
• Features of the IRQ module include:
• A dedicated external interrupt pin (IRQ
)
• IRQ interrupt control bits
• Hysteresis buffer
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Internal pullup resistor
8.3 Functional Description
A low applied to the external interrupt pin can latch a central processor unit (CPU) interrupt request.
Figure 8-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ
pin are latched into the IRQ latch. An interrupt latch remains set until one of
the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the latch that caused the vector fetch.
• Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge
bit in the interrupt status and control register (INTSCR). Writing a 1 to the ACK bit clears the IRQ
latch.
• Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge triggered out of reset and is software-configurable to be either
falling-edge or falling-edge and low-level triggered. The MODE bit in the INTSCR controls the triggering
sensitivity of the IRQ
pin.
When an interrupt pin is edge-triggered only (MODE = 0), the interrupt remains set until a vector fetch,
software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level triggered (MODE = 1), the interrupt remains set
until both of these events occur:
• Vector fetch or software clear
• Return of the interrupt pin to a high level