Datasheet

Input/Output (I/O) Ports
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
148 Freescale Semiconductor
T2CH5–T2CH2 — Timer 2 Channel I/O Bits
The PTF7/T2CH5–PTF4/T2CH2 pins are the TIM2 input capture/output compare pins. The edge/level
select bits, ELSxB:ELSxA, determine whether the PTF7/T2CH5–PTF4/T2CH2 pins are timer channel
I/O pins or general-purpose I/O pins. See Chapter 17 Timer Interface Module (TIM1) and Chapter 18
Timer Interface Module (TIM2).
12.8.2 Data Direction Register F
Data direction register F (DDRF) determines whether each port F pin is an input or an output. Writing a 1
to a DDRF bit enables the output buffer for the corresponding port F pin; a 0 disables the output buffer.
DDRF7–DDRF0 — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears DDRF7–DDRF0, configuring all port F
pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 12-22 shows the port F I/O logic.
Figure 12-22. Port F I/O Circuit
When bit DDRFx is a 1, reading address $0440 reads the PTFx data latch. When bit DDRFx is a 0,
reading address $0440 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-7 summarizes the operation of the port F pins.
Address: $0444
Bit 7654321Bit 0
Read:
DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Write:
Reset:00000000
Figure 12-21. Data Direction Register F (DDRF)
READ DDRF ($0444)
WRITE DDRF ($0444)
RESET
WRITE PTF ($0440)
READ PTD ($0440)
PTFx
DDRFx
PTFx
INTERNAL DATA BUS