Datasheet

ESCI Arbiter
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor 179
13.9.1 ESCI Arbiter Control Register
AM1 and AM0 — Arbiter Mode Select Bits
These read/write bits select the mode of the arbiter module as shown in
Table 13-12. Reset clears AM1 and AM0.
ALOST — Arbitration Lost Flag
This read-only bit indicates loss of arbitration. Clear ALOST by writing a 0 to AM1. Reset clears
ALOST.
ACLK — Arbiter Counter Clock Select Bit
This read/write bit selects the arbiter counter clock source. Reset clears ACLK.
1 = Arbiter counter is clocked with one half of the ESCI input clock generated by the ESCI prescaler
0 = Arbiter counter is clocked with the bus clock divided by four
NOTE
For ACLK = 1, the arbiter input clock is driven from the ESCI prescaler. The
prescaler can be clocked by either the bus clock or CGMXCLK depending
on the state of the SCIBDSRC bit in CONFIG2.
AFIN— Arbiter Bit Time Measurement Finish Flag
This read-only bit indicates bit time measurement has finished. Clear AFIN by writing any value to
SCIACTL. Reset clears AFIN.
1 = Bit time measurement has finished
0 = Bit time measurement not yet finished
ARUN— Arbiter Counter Running Flag
This read-only bit indicates the arbiter counter is running. Reset clears ARUN.
1 = Arbiter counter running
0 = Arbiter counter stopped
Address: $000A
Bit 7654321Bit 0
Read:
AM1
ALOST
AM0 ACLK
AFIN ARUN AROVFL ARD8
Write:
Reset:00000000
= Unimplemented
Figure 13-19. ESCI Arbiter Control Register (SCIACTL)
Table 13-12. ESCI Arbiter Selectable Modes
AM[1:0] ESCI Arbiter Mode
0 0 Idle / counter reset
0 1 Bit time measurement
1 0 Bus arbitration
1 1 Reserved / do not use