Datasheet

System Integration Module (SIM)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
186 Freescale Semiconductor
14.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 14-3. This clock
originates from either an external oscillator or from the on-chip PLL.
14.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four.
14.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST
pin is driven low by the SIM during this entire period. The bus clocks
start upon completion of the timeout.
14.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows CGMXCLK to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. See 14.6.2 Stop Mode.
Figure 14-3. System Clock Signals
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
÷ 2
BUS CLOCK
GENERATORS
SIM
SIM COUNTER
SIMOSCEN
OSCILLATOR (OSC)
OSC2
OSC1
PHASE-LOCKED LOOP (PLL)
CGMXCLK
CGMRCLK
IT12
TO TBM,TIM1,TIM2, ADC,
OSCENINSTOP
FROM
CONFIG
TO REST
OF CHIP
IT23
TO REST
OF CHIP