Datasheet

System Integration Module (SIM)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
188 Freescale Semiconductor
Figure 14-5. Internal Reset Timing
Figure 14-6. Sources of Internal Reset
14.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST
) is held low while the SIM counter counts out
4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
At power-on, these events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
•The RST
pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set.
14.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR) if the COPD bit in the CONFIG1
register is cleared. The SIM actively pulls down the RST
pin for all internal reset sources.
The COP module is disabled if the RST
pin or the IRQ pin is held at V
TST
while the MCU is in monitor
mode. During a break state, V
TST
on the RST pin disables the COP module.
Table 14-2. Reset Recovery
Reset Recovery Type Actual Number of Cycles
POR/LVI 4163 (4096 + 64 + 3)
All others 67 (64 + 3)
RST
RST PULLED LOW BY MCU
IAB
32 CYCLES 32 CYCLES
VECTOR HIGH
CGMXCLK
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
MODRST