Datasheet

Serial Peripheral Interface (SPI) Module
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
206 Freescale Semiconductor
general-purpose I/O not affecting the SPI. (See 15.6.2 Mode Fault Error.) When CPHA = 0, the first
SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first
SPSCK edge, and a falling edge on the SS
pin is used to start the slave data transmission. The slave’s
SS
pin must be toggled back to high and then low again between each byte transmitted as shown in
Figure 15-6.
When CPHA = 0 for a slave, the falling edge of SS
indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of
SS
. Any data written after the falling edge is stored in the transmit data register and transferred to the shift
register after the current transmission.
Figure 15-5. Transmission Format (CPHA = 0)
Figure 15-6. CPHA/SS
Timing
15.4.3 Transmission Format When CPHA = 1
Figure 15-7 shows an SPI transmission in which CPHA = 1. The figure should not be used as a
replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS
line is the slave select input to the slave. The
slave SPI drives its MISO output only when its slave select input (SS
) is low, so that only the selected
slave drives to the master. The SS
pin of the master is not shown but is assumed to be inactive. The SS
pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
15.6.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB
12345678
SPSCK CYCLE #
FOR REFERENCE
SPSCK; CPOL = 0
SPSCK; CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
SS
; TO SLAVE
CAPTURE STROBE
BYTE 1 BYTE 3
MISO/MOSI
BYTE 2
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1