Datasheet

Timer Interface Module (TIM1)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
230 Freescale Semiconductor
17.3.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM1 can generate a PWM
signal. The value in the TIM1 counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM1 counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 17-4 shows, the output compare value in the TIM1 channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM1
to clear the channel pin on output compare if the polarity of the PWM pulse is 1 (ELSxA = 0). Program the
TIM1 to set the pin if the polarity of the PWM pulse is 0 (ELSxA = 1).
The value in the TIM1 counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM1 counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is 000. See 17.8.1 TIM1 Status and Control Register.
The value in the TIM1 channel registers determines the pulse width of the PWM output. The pulse width
of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM1 channel registers
produces a duty cycle of 128/256 or 50%.
Figure 17-4. PWM Period and Pulse Width
17.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 17.3.4 Pulse Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM1 channel registers.
An unsynchronized write to the TIM1 channel registers to change a pulse width value could cause
incorrect operation for up to two PWM periods. For example, writing a new value before the counter
reaches the old value but after the counter reaches the new value prevents any compare during that PWM
period. Also, using a TIM1 overflow interrupt routine to write a new, smaller pulse width value may cause
the compare to be missed. The TIM1 may pass the new value before it is written to the timer channel
(T1CHxH:T1CHxL) registers.
TCHx
PERIOD
PULSE
WIDTH
OVERFLOW OVERFLOW OVERFLOW
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
TCHx
POLARITY = 1
(ELSxA = 0)
POLARITY = 0
(ELSxA = 1)