Datasheet
Table Of Contents
- Revision History
- List of Chapters
- Table of Contents
- Chapter 1 General Description
- 1.1 Introduction
- 1.2 Features
- 1.3 MCU Block Diagram
- 1.4 Pin Assignments
- 1.5 Pin Functions
- 1.5.1 Power Supply Pins (VDD and VSS)
- 1.5.2 Oscillator Pins (OSC1 and OSC2)
- 1.5.3 External Reset Pin (RST)
- 1.5.4 External Interrupt Pin (IRQ)
- 1.5.5 CGM Power Supply Pins (VDDA and VSSA)
- 1.5.6 External Filter Capacitor Pin (CGMXFC)
- 1.5.7 ADC Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL)
- 1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7/AD15-PTA0/KBD0/AD8)
- 1.5.9 Port B I/O Pins (PTB7/AD7-PTB0/AD0)
- 1.5.10 Port C I/O Pins (PTC6-PTC0)
- 1.5.11 Port D I/O Pins (PTD7/T2CH1-PTD0/SS)
- 1.5.12 Port E I/O Pins (PTE5-PTE2, PTE1/RxD, and PTE0/TxD)
- 1.5.13 Port F I/O Pins (PTF7/T2CH5-PTF0)
- 1.5.14 Port G I/O Pins (PTG7/AD23-PTBG0/AD16)
- 1.5.15 Unused Pin Termination
- Chapter 2 Memory
- 2.1 Introduction
- 2.2 Unimplemented Memory Locations
- 2.3 Reserved Memory Locations
- 2.4 Input/Output (I/O) Section
- 2.5 Random-Access Memory (RAM)
- 2.6 FLASH-1 Memory (FLASH-1)
- 2.7 FLASH-2 Memory (FLASH-2)
- Chapter 3 Analog-to-Digital Converter (ADC)
- Chapter 4 Clock Generator Module (CGM)
- 4.1 Introduction
- 4.2 Features
- 4.3 Functional Description
- 4.4 I/O Signals
- 4.4.1 Crystal Amplifier Input Pin (OSC1)
- 4.4.2 Crystal Amplifier Output Pin (OSC2)
- 4.4.3 External Filter Capacitor Pin (CGMXFC)
- 4.4.4 PLL Analog Power Pin (Vdda)
- 4.4.5 PLL Analog Ground Pin (Vssa)
- 4.4.6 Oscillator Enable Signal (SIMOSCEN)
- 4.4.7 Oscillator Enable in Stop Mode Bit (OSCENINSTOP)
- 4.4.8 Crystal Output Frequency Signal (CGMXCLK)
- 4.4.9 CGM Base Clock Output (CGMOUT)
- 4.4.10 CGM CPU Interrupt (CGMINT)
- 4.5 CGM Registers
- 4.6 Interrupts
- 4.7 Special Modes
- 4.8 Acquisition/Lock Time Specifications
- Chapter 5 Configuration Register (CONFIG)
- Chapter 6 Computer Operating Properly (COP) Module
- Chapter 7 Central Processor Unit (CPU)
- Chapter 8 External Interrupt (IRQ)
- Chapter 9 Keyboard Interrupt Module (KBI)
- Chapter 10 Low-Power Modes
- 10.1 Introduction
- 10.2 Analog-to-Digital Converter (ADC)
- 10.3 Break Module (BRK)
- 10.4 Central Processor Unit (CPU)
- 10.5 Clock Generator Module (CGM)
- 10.6 Computer Operating Properly Module (COP)
- 10.7 External Interrupt Module (IRQ)
- 10.8 Keyboard Interrupt Module (KBI)
- 10.9 Low-Voltage Inhibit Module (LVI)
- 10.10 Enhanced Serial Communications Interface Module (ESCI)
- 10.11 Serial Peripheral Interface Module (SPI)
- 10.12 Timer Interface Module (TIM1 and TIM2)
- 10.13 Timebase Module (TBM)
- 10.14 Exiting Wait Mode
- 10.15 Exiting Stop Mode
- Chapter 11 Low-Voltage Inhibit (LVI)
- Chapter 12 Input/Output (I/O) Ports
- Chapter 13 Enhanced Serial Communications Interface (ESCI) Module
- Chapter 14 System Integration Module (SIM)
- Chapter 15 Serial Peripheral Interface (SPI) Module
- Chapter 16 Timebase Module (TBM)
- Chapter 17 Timer Interface Module (TIM1)
- Chapter 18 Timer Interface Module (TIM2)
- Chapter 19 Development Support
- Chapter 20 Electrical Specifications
- 20.1 Introduction
- 20.2 Absolute Maximum Ratings
- 20.3 Functional Operating Range
- 20.4 Thermal Characteristics
- 20.5 5.0-Vdc Electrical Characteristics
- 20.6 3.3-Vdc Electrical Characteristics
- 20.7 5.0-Volt Control Timing
- 20.8 3.3-Volt Control Timing
- 20.9 Clock Generation Module (CGM) Characteristics
- 20.10 5.0-Volt ADC Characteristics
- 20.11 3.3-Volt ADC Characteristics
- 20.12 5.0-Volt SPI Characteristics
- 20.13 3.3-Volt SPI Characteristics
- 20.14 Timer Interface Module Characteristics
- 20.15 Memory Characteristics
- Chapter 21 Ordering Information and Mechanical Specifications
- Appendix A MC68HC908GR48A
- Appendix B MC68HC908GR32A
Timer Interface Module (TIM2)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
252 Freescale Semiconductor
18.7 I/O Signals
Port D shares two of its pins with the TIM2. Port F shares four of its pins with the TIM2. PTD6/T2CH0 is
an external clock input to the TIM2 prescaler. The six TIM2 channel I/O pins are PTD6/T2CH0,
PTD7/T2CH1, PTF4/T2CH2, PTF5/T2CH3, PTF6/T2CH4, and PTF7/T2CH5.
18.7.1 TIM2 Clock Pin (T2CH0)
T2CH0 is an external clock input that can be the clock source for the TIM2 counter instead of the
prescaled internal bus clock. Select the T2CH0
input by writing 1s to the three prescaler select bits,
PS[2:0]. (See 18.8.1 TIM2 Status and Control Register.) The minimum TCLK pulse width is specified in
20.14 Timer Interface Module Characteristics. The maximum TCLK frequency is the least: 4 MHz or bus
frequency ÷ 2.
When the PTD6/T2CH0 pin is the TIM2 clock input, it is an input regardless of the state of the DDRD6 bit
in data direction register D.
18.7.2 TIM2 Channel I/O Pins (T2CH5:T2CH2 and T2CH1:T2CH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
T2CH0, T2CH2, and T2CH4 can be configured as buffered output compare or buffered PWM pins.
18.8 I/O Registers
These I/O registers control and monitor TIM2 operation:
• TIM2 status and control register (T2SC)
• TIM2 counter registers (T2CNTH:T2CNTL)
• TIM2 counter modulo registers (T2MODH:T2MODL)
• TIM2 channel status and control registers (T2SC0, T2SC1, T2SC2, T2SC3, T2SC4, and T2SC5)
• TIM2 channel registers (T2CH0H:T2CH0L, T2CH1H:T2CH1L, T2CH2H:T2CH2L,
T2CH3H:T2CH3L, T2CH4H:T2CH4L, and T2CH5H:T2CH5L)
18.8.1 TIM2 Status and Control Register
The TIM2 status and control register:
• Enables TIM2 overflow interrupts
• Flags TIM2 overflows
• Stops the TIM2 counter
• Resets the TIM2 counter
• Prescales the TIM2 counter clock
Address: $002B
Bit 7654321Bit 0
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
= Unimplemented
Figure 18-5. TIM2 Status and Control Register (T2SC)