Datasheet

I/O Registers
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor 257
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port D or port F, and pin
PTDx/T2CHx or pin PTFx/T2CHx is available as a general- purpose I/O pin. Table 18-2 shows how
ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
NOTE
After initially enabling a TIM2 channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM2 counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM2 counter overflow.
0 = Channel x pin does not toggle on TIM2 counter overflow.
NOTE
When TOVx is set, a TIM2 counter overflow takes precedence over a
channel x output compare if both occur at the same time.
Table 18-2. Mode, Edge, and Level Selection
MSxB MSxA ELSxB ELSxA Mode Configuration
X0 0 0
Output preset
Pin under port control;
initial output level high
X1 0 0
Pin under port control;
initial output level low
00 0 1
Input capture
Capture on rising edge only
0 0 1 0 Capture on falling edge only
00 1 1
Capture on rising
or falling edge
01 0 0
Output compare
or PWM
Software compare only
0 1 0 1 Toggle output on compare
0 1 1 0 Clear output on compare
0 1 1 1 Set output on compare
1 X 0 1 Buffered
output
compare or
buffered PWM
Toggle output on compare
1 X 1 0 Clear output on compare
1 X 1 1 Set output on compare