Datasheet

Monitor Module (MON)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor 267
19.3 Monitor Module (MON)
The monitor module allows debugging and programming of the microcontroller unit (MCU) through a
single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher
test voltage, V
TST
, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware
requirements for in-circuit programming.
Features of the monitor module include:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between MCU and host computer
• Standard non-return-to-zero (NRZ) communication with host computer
• Standard communication baud rate (7200 @ 2-MHz bus frequency)
• Execution of code in random-access memory (RAM) or FLASH
• FLASH memory security feature
(1)
• FLASH memory programming interface
• Monitor mode entry without high voltage, V
TST
, if reset vector is blank ($FFFE and $FFFF contain
$FF)
• Normal monitor mode entry if V
TST
is applied to IRQ
19.3.1 Functional Description
Figure 19-9 shows a simplified diagram of the monitor mode.
The monitor module receives and executes commands from a host computer.
Figure 19-10 and Figure 19-11 show example circuits used to enter monitor mode and communicate with
a host computer via a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
Table 19-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication at 7200 baud provided one
of the following sets of conditions is met:
• If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 4.0 MHz (7200 baud)
–PTB4 = low
–IRQ
= V
TST
• If $FFFE and $FFFF do not contain $FF (programmed state):
– The external clock is 8.0 MHz (7200 baud)
– PTB4 = high
– IRQ = V
TST
• If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 8.0 MHz (7200 baud)
–IRQ
= V
DD
(this can be implemented through the internal IRQ pullup) or V
SS
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.