Datasheet
Table Of Contents
- Revision History
- List of Chapters
- Table of Contents
- Chapter 1 General Description
- 1.1 Introduction
- 1.2 Features
- 1.3 MCU Block Diagram
- 1.4 Pin Assignments
- 1.5 Pin Functions
- 1.5.1 Power Supply Pins (VDD and VSS)
- 1.5.2 Oscillator Pins (OSC1 and OSC2)
- 1.5.3 External Reset Pin (RST)
- 1.5.4 External Interrupt Pin (IRQ)
- 1.5.5 CGM Power Supply Pins (VDDA and VSSA)
- 1.5.6 External Filter Capacitor Pin (CGMXFC)
- 1.5.7 ADC Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL)
- 1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7/AD15-PTA0/KBD0/AD8)
- 1.5.9 Port B I/O Pins (PTB7/AD7-PTB0/AD0)
- 1.5.10 Port C I/O Pins (PTC6-PTC0)
- 1.5.11 Port D I/O Pins (PTD7/T2CH1-PTD0/SS)
- 1.5.12 Port E I/O Pins (PTE5-PTE2, PTE1/RxD, and PTE0/TxD)
- 1.5.13 Port F I/O Pins (PTF7/T2CH5-PTF0)
- 1.5.14 Port G I/O Pins (PTG7/AD23-PTBG0/AD16)
- 1.5.15 Unused Pin Termination
- Chapter 2 Memory
- 2.1 Introduction
- 2.2 Unimplemented Memory Locations
- 2.3 Reserved Memory Locations
- 2.4 Input/Output (I/O) Section
- 2.5 Random-Access Memory (RAM)
- 2.6 FLASH-1 Memory (FLASH-1)
- 2.7 FLASH-2 Memory (FLASH-2)
- Chapter 3 Analog-to-Digital Converter (ADC)
- Chapter 4 Clock Generator Module (CGM)
- 4.1 Introduction
- 4.2 Features
- 4.3 Functional Description
- 4.4 I/O Signals
- 4.4.1 Crystal Amplifier Input Pin (OSC1)
- 4.4.2 Crystal Amplifier Output Pin (OSC2)
- 4.4.3 External Filter Capacitor Pin (CGMXFC)
- 4.4.4 PLL Analog Power Pin (Vdda)
- 4.4.5 PLL Analog Ground Pin (Vssa)
- 4.4.6 Oscillator Enable Signal (SIMOSCEN)
- 4.4.7 Oscillator Enable in Stop Mode Bit (OSCENINSTOP)
- 4.4.8 Crystal Output Frequency Signal (CGMXCLK)
- 4.4.9 CGM Base Clock Output (CGMOUT)
- 4.4.10 CGM CPU Interrupt (CGMINT)
- 4.5 CGM Registers
- 4.6 Interrupts
- 4.7 Special Modes
- 4.8 Acquisition/Lock Time Specifications
- Chapter 5 Configuration Register (CONFIG)
- Chapter 6 Computer Operating Properly (COP) Module
- Chapter 7 Central Processor Unit (CPU)
- Chapter 8 External Interrupt (IRQ)
- Chapter 9 Keyboard Interrupt Module (KBI)
- Chapter 10 Low-Power Modes
- 10.1 Introduction
- 10.2 Analog-to-Digital Converter (ADC)
- 10.3 Break Module (BRK)
- 10.4 Central Processor Unit (CPU)
- 10.5 Clock Generator Module (CGM)
- 10.6 Computer Operating Properly Module (COP)
- 10.7 External Interrupt Module (IRQ)
- 10.8 Keyboard Interrupt Module (KBI)
- 10.9 Low-Voltage Inhibit Module (LVI)
- 10.10 Enhanced Serial Communications Interface Module (ESCI)
- 10.11 Serial Peripheral Interface Module (SPI)
- 10.12 Timer Interface Module (TIM1 and TIM2)
- 10.13 Timebase Module (TBM)
- 10.14 Exiting Wait Mode
- 10.15 Exiting Stop Mode
- Chapter 11 Low-Voltage Inhibit (LVI)
- Chapter 12 Input/Output (I/O) Ports
- Chapter 13 Enhanced Serial Communications Interface (ESCI) Module
- Chapter 14 System Integration Module (SIM)
- Chapter 15 Serial Peripheral Interface (SPI) Module
- Chapter 16 Timebase Module (TBM)
- Chapter 17 Timer Interface Module (TIM1)
- Chapter 18 Timer Interface Module (TIM2)
- Chapter 19 Development Support
- Chapter 20 Electrical Specifications
- 20.1 Introduction
- 20.2 Absolute Maximum Ratings
- 20.3 Functional Operating Range
- 20.4 Thermal Characteristics
- 20.5 5.0-Vdc Electrical Characteristics
- 20.6 3.3-Vdc Electrical Characteristics
- 20.7 5.0-Volt Control Timing
- 20.8 3.3-Volt Control Timing
- 20.9 Clock Generation Module (CGM) Characteristics
- 20.10 5.0-Volt ADC Characteristics
- 20.11 3.3-Volt ADC Characteristics
- 20.12 5.0-Volt SPI Characteristics
- 20.13 3.3-Volt SPI Characteristics
- 20.14 Timer Interface Module Characteristics
- 20.15 Memory Characteristics
- Chapter 21 Ordering Information and Mechanical Specifications
- Appendix A MC68HC908GR48A
- Appendix B MC68HC908GR32A
3.3-Vdc Electrical Characteristics
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor 281
20.6 3.3-Vdc Electrical Characteristics
Characteristic
(1)
Symbol Min
Typ
(2)
Max Unit
Output high voltage
(I
Load
= –0.6 mA) all I/O pins
(I
Load
= –4.0 mA) all I/O pins
(I
Load
= –10.0 mA) pins PTC0–PTC4, PTF0–PTF3 only
Maximum combined I
OH
for port PTA7–PTA3,
port PTC0–PTC1, port E, port PTD0–PTD3,
port PTF0–PTF3, port PTG4–PTG7
Maximum combined I
OH
for port PTA2–PTA0,
port B, port PTC2–PTC6, port PTD4–PTD7
port PTF4–PTF7, port PTG0–PTG3
Maximum total I
OH
for all port pins
V
OH
V
OH
V
OH
I
OH1
I
OH2
I
OHT
V
DD
– 0.3
V
DD
– 1.0
V
DD
– 1.0
—
—
—
—
—
—
—
—
—
—
—
—
30
30
60
V
V
V
mA
mA
mA
Output low voltage
(I
Load
= 0.5 mA) all I/O pins
(I
Load
= 5 mA) all I/O pins
(I
Load
= 10 mA) pins PTC0–PTC4, PTF0–PTF3 only
Maximum combined I
OH
for port PTA7–PTA3,
port PTC0–PTC1, port E, port PTD0–PTD3
port PTF0–PTF3, port PTG4–PTG7
Maximum combined I
OH
for port PTA2–PTA0,
port B, port PTC2–PTC6, port PTD4–PTD7
port PTF4–PTF7, port PTG0–PTG3
Maximum total I
OL
for all port pins
V
OL
V
OL
V
OL
I
OL1
I
OL2
I
OLT
—
—
—
—
—
—
—
—
—
—
—
—
0.3
1.0
0.8
30
30
60
V
V
V
mA
mA
mA
Input high voltage
All ports, IRQ
, RST, OSC1
V
IH
0.7 × V
DD
—
V
DD
V
Input low voltage
All ports, IRQ, RST, OSC1
V
IL
V
SS
—
0.3 × V
DD
V
V
DD
supply current
Run
(3)
Wait
(4)
Stop
(5)
Stop with TBM enabled
(6)
Stop with LVI and TBM enabled
(6)
Stop with LVI
I
DD
—
—
—
—
—
—
8
3
0.5
500
700
200
12
6
6
700
900
300
mA
mA
μA
μA
μA
μA
DC injection current
(7)
(8)
(9)
(10)
Single pin limit
V
in
> V
DD
V
in
< V
SS
Total MCU limit, includes sum of all stressed pins
V
in
> V
DD
V
in
< V
SS
I
IC
0
0
0
0
—
—
—
—
2
–0.2
25
–5
mA
I/O ports Hi-Z leakage current
(11)
I
IL
0—±1 μA
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