Datasheet

Electrical Specifications
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
282 Freescale Semiconductor
Pullup/pulldown resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
R
PU
20 45 65 kΩ
Capacitance
Ports (as input or output)
C
Out
C
In
—
—
—
—
12
8
pF
Monitor mode entry voltage
V
TST
V
DD
+ 2.5
—
V
DD
+ 4.0
V
Low-voltage inhibit, trip falling voltage
V
TRIPF
2.35 2.6 2.8 V
Low-voltage inhibit, trip rising voltage
V
TRIPR
2.4 2.66 2.9 V
Low-voltage inhibit reset/recover hysteresis
(V
TRIPF
+ V
HYS
= V
TRIPR
)
V
HYS
—100 —mV
POR rearm voltage
(12)
V
POR
0 — 100 mV
POR reset voltage
(13)
V
PORRST
0 700 800 mV
POR rise time ramp rate
(14)
R
POR
0.02 — — V/ms
1. V
DD
= 3.3 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= T
A
(min) to T
A
(max), unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) I
DD
measured using external square wave clock source (f
OSC
= 16 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run I
DD
. Measured with all modules enabled.
4. Wait I
DD
measured using external square wave clock source (f
OSC
= 16 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
I
DD
. Measured with CGM and LVI enabled.
5. Stop I
DD
is measured with OSC1 = V
SS
. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All ports
configured as inputs. Typical values at midpoint of voltage range, 25°C only.
6. Stop I
DD
with TBM enabled is measured using an external square wave clock source (f
OSC
= 4 MHz). All inputs 0.2 V from
rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. This parameter is characterized and not tested on each device.
8. All functional non-supply pins are internally clamped to V
SS
and V
DD
.
9. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
10. Power supply must maintain regulation within operating V
DD
range during instantaneous and operating maximum current
conditions. If positive injection current (V
in
> V
DD
) is greater than I
DD
, the injection current may flow out of V
DD
and could
result in external power supply going out of regulation. Ensure external V
DD
load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock
is present, or if clock rate is very low (which would reduce overall power consumption).
11. Pullups and pulldowns are disabled.
12. Maximum is highest voltage that POR is guaranteed.
13. Maximum is highest voltage that POR is possible.
14. If minimum V
DD
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
DD
is reached.
Characteristic
(1)
Symbol Min
Typ
(2)
Max Unit