Datasheet

Clock Generation Module (CGM) Characteristics
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor 285
20.9.3 CGM Acquisition/Lock Time Information
Characteristic Symbol Min Typ Max Unit
Acquisition mode entry frequency tolerance
(1)
1. Deviation between VCO frequency and desired frequency to enter PLL acquisition mode.
Δ
ACQ
± 3.6 — ± 7.2 %
Tracking mode entry frequency tolerance
(2)
2. Deviation between VCO frequency and desired frequency to enter PLL tracking mode (stable).
Δ
TRK
0—± 3.6 %
LOCK entry frequency tolerance
(3)
3. Deviation between VCO frequency and desired frequency to enter locked mode.
Δ
LOCK
0—± 0.9 %
LOCK exit frequency tolerance
(4)
4. Deviation between VCO frequency and desired frequency to exit locked mode.
Δ
UNL
± 0.9 — ± 1.8 %
Reference cycles per acquisition mode period
n
ACQ
—32—
Reference cycles per tracking mode period
n
TRK
— 128 —
Automatic mode time to stable
t
ACQ
n
ACQ
/f
RCLK
See note
(5)
5. Acquisition time is an integer multiple of reference cycles divided by reference clock.
—s
Automatic stable to lock time
t
AL
n
TRK
/f
RCLK
See note
(6)
6. Stable to lock time is an integer multiple of reference cycles divided by reference clock.
—s
Automatic lock time (t
ACQ
+ t
AL
)
(7)
7. Maximum lock time depends on CGMXFC filter components, power supply filtering, and reference clock stability. PLL may
not lock if improper components or poor filtering and layout are used.
t
LOCK
—525ms
PLL jitter, deviation of average bus frequency
over 2 ms period
f
J
0—
f
RCLK
x
0.025% x
N/4
Hz