Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 48 (7x7) 8-Bit 8 MHz I/O number 37

Table Of Contents

Revision History
List of Chapters
Table of Contents
Chapter 1 General Description
- 1.1 Introduction
- 1.2 Features
  - 1.2.1 Standard Features
  - 1.2.2 Features of the CPU08
- 1.3 MCU Block Diagram
- 1.4 Pin Assignments
- 1.5 Pin Functions
Chapter 2 Memory
- 2.1 Introduction
- 2.2 Unimplemented Memory Locations
- 2.3 Reserved Memory Locations
- 2.4 Input/Output (I/O) Section
- 2.5 Random-Access Memory (RAM)
- 2.6 FLASH-1 Memory (FLASH-1)
- 2.7 FLASH-2 Memory (FLASH-2)
Chapter 3 Analog-to-Digital Converter (ADC)
- 3.1 Introduction
- 3.2 Features
- 3.3 Functional Description
- 3.4 Monotonicity
- 3.5 Interrupts
- 3.6 Low-Power Modes
  - 3.6.1 Wait Mode
  - 3.6.2 Stop Mode
- 3.7 I/O Signals
- 3.8 I/O Registers
Chapter 4 Clock Generator Module (CGM)
- 4.1 Introduction
- 4.2 Features
- 4.3 Functional Description
- 4.4 I/O Signals
- 4.5 CGM Registers
- 4.6 Interrupts
- 4.7 Special Modes
- 4.8 Acquisition/Lock Time Specifications
Chapter 5 Configuration Register (CONFIG)
- 5.1 Introduction
- 5.2 Functional Description
Chapter 6 Computer Operating Properly (COP) Module
- 6.1 Introduction
- 6.2 Functional Description
- 6.3 I/O Signals
- 6.4 COP Control Register
- 6.5 Interrupts
- 6.6 Monitor Mode
- 6.7 Low-Power Modes
  - 6.7.1 Wait Mode
  - 6.7.2 Stop Mode
- 6.8 COP Module During Break Mode
Chapter 7 Central Processor Unit (CPU)
- 7.1 Introduction
- 7.2 Features
- 7.3 CPU Registers
- 7.4 Arithmetic/Logic Unit (ALU)
- 7.5 Low-Power Modes
  - 7.5.1 Wait Mode
  - 7.5.2 Stop Mode
- 7.6 CPU During Break Interrupts
- 7.7 Instruction Set Summary
- 7.8 Opcode Map
Chapter 8 External Interrupt (IRQ)
- 8.1 Introduction
- 8.2 Features
- 8.3 Functional Description
- 8.4 IRQ Pin
- 8.5 IRQ Module During Break Interrupts
- 8.6 IRQ Status and Control Register
Chapter 9 Keyboard Interrupt Module (KBI)
- 9.1 Introduction
- 9.2 Features
- 9.3 Functional Description
- 9.4 Keyboard Initialization
- 9.5 Low-Power Modes
  - 9.5.1 Wait Mode
  - 9.5.2 Stop Mode
- 9.6 Keyboard Module During Break Interrupts
- 9.7 I/O Registers
Chapter 10 Low-Power Modes
- 10.1 Introduction
  - 10.1.1 Wait Mode
  - 10.1.2 Stop Mode
- 10.2 Analog-to-Digital Converter (ADC)
  - 10.2.1 Wait Mode
  - 10.2.2 Stop Mode
- 10.3 Break Module (BRK)
  - 10.3.1 Wait Mode
  - 10.3.2 Stop Mode
- 10.4 Central Processor Unit (CPU)
  - 10.4.1 Wait Mode
  - 10.4.2 Stop Mode
- 10.5 Clock Generator Module (CGM)
  - 10.5.1 Wait Mode
  - 10.5.2 Stop Mode
- 10.6 Computer Operating Properly Module (COP)
  - 10.6.1 Wait Mode
  - 10.6.2 Stop Mode
- 10.7 External Interrupt Module (IRQ)
  - 10.7.1 Wait Mode
  - 10.7.2 Stop Mode
- 10.8 Keyboard Interrupt Module (KBI)
  - 10.8.1 Wait Mode
  - 10.8.2 Stop Mode
- 10.9 Low-Voltage Inhibit Module (LVI)
  - 10.9.1 Wait Mode
  - 10.9.2 Stop Mode
- 10.10 Enhanced Serial Communications Interface Module (ESCI)
  - 10.10.1 Wait Mode
  - 10.10.2 Stop Mode
- 10.11 Serial Peripheral Interface Module (SPI)
  - 10.11.1 Wait Mode
  - 10.11.2 Stop Mode
- 10.12 Timer Interface Module (TIM1 and TIM2)
  - 10.12.1 Wait Mode
  - 10.12.2 Stop Mode
- 10.13 Timebase Module (TBM)
  - 10.13.1 Wait Mode
  - 10.13.2 Stop Mode
- 10.14 Exiting Wait Mode
- 10.15 Exiting Stop Mode
Chapter 11 Low-Voltage Inhibit (LVI)
- 11.1 Introduction
- 11.2 Features
- 11.3 Functional Description
- 11.4 LVI Status Register
- 11.5 LVI Interrupts
- 11.6 Low-Power Modes
  - 11.6.1 Wait Mode
  - 11.6.2 Stop Mode
Chapter 12 Input/Output (I/O) Ports
- 12.1 Introduction
- 12.2 Unused Pin Termination
- 12.3 Port A
- 12.4 Port B
  - 12.4.1 Port B Data Register
  - 12.4.2 Data Direction Register B
- 12.5 Port C
- 12.6 Port D
- 12.7 Port E
  - 12.7.1 Port E Data Register
  - 12.7.2 Data Direction Register E
- 12.8 Port F
  - 12.8.1 Port F Data Register
  - 12.8.2 Data Direction Register F
- 12.9 Port G
  - 12.9.1 Port G Data Register
  - 12.9.2 Data Direction Register G
Chapter 13 Enhanced Serial Communications Interface (ESCI) Module
- 13.1 Introduction
- 13.2 Features
- 13.3 Pin Name Conventions
- 13.4 Functional Description
- 13.5 Low-Power Modes
  - 13.5.1 Wait Mode
  - 13.5.2 Stop Mode
- 13.6 ESCI During Break Module Interrupts
- 13.7 I/O Signals
  - 13.7.1 PTE0/TxD (Transmit Data)
  - 13.7.2 PTE1/RxD (Receive Data)
- 13.8 I/O Registers
- 13.9 ESCI Arbiter
Chapter 14 System Integration Module (SIM)
- 14.1 Introduction
- 14.2 SIM Bus Clock Control and Generation
- 14.3 Reset and System Initialization
  - 14.3.1 External Pin Reset
  - 14.3.2 Active Resets from Internal Sources
- 14.4 SIM Counter
- 14.5 Exception Control
- 14.6 Low-Power Modes
  - 14.6.1 Wait Mode
  - 14.6.2 Stop Mode
- 14.7 SIM Registers
Chapter 15 Serial Peripheral Interface (SPI) Module
- 15.1 Introduction
- 15.2 Features
- 15.3 Functional Description
  - 15.3.1 Master Mode
  - 15.3.2 Slave Mode
- 15.4 Transmission Formats
- 15.5 Queuing Transmission Data
- 15.6 Error Conditions
  - 15.6.1 Overflow Error
  - 15.6.2 Mode Fault Error
- 15.7 Interrupts
- 15.8 Resetting the SPI
- 15.9 Low-Power Modes
  - 15.9.1 Wait Mode
  - 15.9.2 Stop Mode
- 15.10 SPI During Break Interrupts
- 15.11 I/O Signals
- 15.12 I/O Registers
Chapter 16 Timebase Module (TBM)
- 16.1 Introduction
- 16.2 Features
- 16.3 Functional Description
- 16.4 Interrupts
- 16.5 TBM Interrupt Rate
- 16.6 Low-Power Modes
  - 16.6.1 Wait Mode
  - 16.6.2 Stop Mode
- 16.7 Timebase Control Register
Chapter 17 Timer Interface Module (TIM1)
- 17.1 Introduction
- 17.2 Features
- 17.3 Functional Description
- 17.4 Interrupts
- 17.5 Wait Mode
- 17.6 TIM1 During Break Interrupts
- 17.7 Input/Output Signals
- 17.8 Input/Output Registers
Chapter 18 Timer Interface Module (TIM2)
- 18.1 Introduction
- 18.2 Features
- 18.3 Functional Description
- 18.4 Interrupts
- 18.5 Low-Power Modes
  - 18.5.1 Wait Mode
  - 18.5.2 Stop Mode
- 18.6 TIM2 During Break Interrupts
- 18.7 I/O Signals
  - 18.7.1 TIM2 Clock Pin (T2CH0)
  - 18.7.2 TIM2 Channel I/O Pins (T2CH5:T2CH2 and T2CH1:T2CH0)
- 18.8 I/O Registers
Chapter 19 Development Support
- 19.1 Introduction
- 19.2 Break Module (BRK)
- 19.3 Monitor Module (MON)
  - 19.3.1 Functional Description
  - 19.3.2 Security
Chapter 20 Electrical Specifications
- 20.1 Introduction
- 20.2 Absolute Maximum Ratings
- 20.3 Functional Operating Range
- 20.4 Thermal Characteristics
- 20.5 5.0-Vdc Electrical Characteristics
- 20.6 3.3-Vdc Electrical Characteristics
- 20.7 5.0-Volt Control Timing
- 20.8 3.3-Volt Control Timing
- 20.9 Clock Generation Module (CGM) Characteristics
- 20.10 5.0-Volt ADC Characteristics
- 20.11 3.3-Volt ADC Characteristics
- 20.12 5.0-Volt SPI Characteristics
- 20.13 3.3-Volt SPI Characteristics
- 20.14 Timer Interface Module Characteristics
- 20.15 Memory Characteristics
Chapter 21 Ordering Information and Mechanical Specifications
- 21.1 Introduction
- 21.2 MC Order Numbers
- 21.3 Package Dimensions
Appendix A MC68HC908GR48A
- A.1 Introduction
- A.2 Block Diagram
- A.3 Memory
- A.4 Ordering Information
Appendix B MC68HC908GR32A
- B.1 Introduction
- B.2 Block Diagram
- B.3 Memory
- B.4 Ordering Information

Memory

MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5

48 Freescale Semiconductor

E. The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH

address programmed to clearing the PGM bit (step 7 to step 10) must not exceed the maximum

programming time, t

PROG

maximum.

F. Be cautious when programming the FLASH-1 array to ensure that non-FLASH locations are not used

as the address that is written to when selecting either the desired row address range in step 3 of the

algorithm or the byte to be programmed in step 7 of the algorithm.

2.6.7 Low-Power Modes

The WAIT and STOP instructions will place the MCU in low power-consumption standby modes.

2.6.7.1 Wait Mode

Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the

FLASH memory directly; however, no memory activity will take place since the CPU is inactive.

The WAIT instruction should not be executed while performing a program or erase operation on the

FLASH. Wait mode will suspend any FLASH program/erase operations and leave the memory in a

standby mode.

2.6.7.2 Stop Mode

Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the

FLASH memory directly; however, no memory activity will take place since the CPU is inactive.

The STOP instruction should not be executed while performing a program or erase operation on the

FLASH. Stop mode will suspend any FLASH program/erase operations and leave the memory in a

standby mode.

NOTE

Standby mode is the power saving mode of the FLASH module, in which all

internal control signals to the FLASH are inactive and the current

consumption of the FLASH is minimum.