Datasheet

I/O Registers
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor 65
3.7.4 ADC Voltage Reference Low Pin (V
REFL
)
The ADC analog portion uses V
REFL
as its lower voltage reference pin. By default, connect the V
REFL
pin
to the same voltage potential as V
SS
. External filtering is often necessary to ensure a clean V
REFL
for good
results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values.
NOTE
For maximum noise immunity, route V
REFL
carefully and, if not connected
to V
SS
, place bypass capacitors as close as possible to the package.
Routing V
REFH
close and parallel to V
REFL
may improve common mode
noise rejection.
V
SSAD
and V
REFL
are bonded internally.
3.7.5 ADC Voltage In (V
ADIN
)
V
ADIN
is the input voltage signal from one of the 24 ADC channels to the ADC module.
3.8 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADRH and ADRL)
• ADC clock register (ADCLK)
3.8.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described here.
COCO — Conversions Complete Bit
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion.
COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It
always reads as a 0.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1)
NOTE
The write function of the COCO bit is reserved. When writing to the ADSCR
register, always have a 0 in the COCO bit position.
Address: $003C
Bit 7654321Bit 0
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write: R
Reset:00011111
R= Reserved
Figure 3-4. ADC Status and Control Register (ADSCR)