Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
66 Freescale Semiconductor
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared.
Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH4–ADCH0 — ADC Channel Select Bits
ADCH4–ADCH0 form a 5-bit field which is used to select one of 32 ADC channels. Only 24 channels,
AD23–AD0, are available on this MCU. The channels are detailed in Table 3-1. Care should be taken
when using a port pin as both an analog and digital input simultaneously to prevent switching noise
from corrupting the analog signal. See Table 3-1.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not being used.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
The voltage levels supplied from internal reference nodes, as specified in
Table 3-1, are used to verify the operation of the ADC converter both in production test and for user
applications.
Table 3-1. Mux Channel Select
(1)
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select
00000 PTB0/AD0
00001 PTB1/AD1
00010 PTB2/AD2
00011 PTB3/AD3
00100 PTB4/AD4
00101 PTB5/AD5
00110 PTB6/AD6
00111 PTB7/AD7
0 1 0 0 0 PTA0/KBD0/AD8
0 1 0 0 1 PTA1/KBD1/AD9
0 1 0 1 0 PTA2/KBD2/AD10
0 1 0 1 1 PTA3/KBD3/AD11
0 1 1 0 0 PTA4/KBD4/AD12
0 1 1 0 1 PTA5/KBD5/AD13
0 1 1 1 0 PTA6/KBD6/AD14
0 1 1 1 1 PTA7/KBD7/AD15
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