Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
68 Freescale Semiconductor
3.8.2.2 Right Justified Mode
In right justified mode, the ADRH register holds the two MSBs of the
10-bit result. All other bits read as 0. The ADRL register holds the eight LSBs of the 10-bit result. ADRH
and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches
the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL
reads are completed.
3.8.2.3 Left Justified Signed Data Mode
In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only
difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two
LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single
channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All
subsequent results will be lost until the ADRH and ADRL reads are completed.
Address: $003D ADRH
Bit 7654321Bit 0
Read:000000AD9AD8
Write:
Reset: Unaffected by reset
Address: $003E ADRL
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL)
Address: $003D
Bit 7654321Bit 0
Read: AD9
AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:
Reset: Unaffected by reset
Address: $003E
Read:AD1AD0000000
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 3-7. ADC Data Register High (ADRH) and Low (ADRL)