Datasheet

I/O Registers
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor 69
3.8.2.4 Eight Bit Truncation Mode
In 8-bit truncation mode, the ADRL register holds the eight MSBs of the 10-bit result. The ADRH register
is unused and reads as 0. The ADRL register is updated each time an ADC single channel conversion
completes. In 8-bit mode, the ADRL register contains no interlocking with ADRH.
3.8.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Address: $003D ADRH
Bit 7654321Bit 0
Read:00000000
Write:
Reset: Unaffected by reset
Address: $003E ADRL
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 3-8. ADC Data Register High (ADRH) and Low (ADRL)
Address: $003F
Bit 7654321Bit 0
Read:
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 R
0
Write:
Reset:00000100
= Unimplemented R = Reserved
Figure 3-9. ADC Clock Register (ADCLK)
Table 3-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC input clock ÷ 1
0 0 1 ADC input clock ÷ 2
0 1 0 ADC input clock ÷ 4
0 1 1 ADC input clock ÷ 8
1
X
(1)
1. X = Don’t care
X
(1)
ADC input clock ÷ 16