Datasheet

Functional Description
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor 75
The following conditions apply when in manual mode:
•ACQ
is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ
bit must be clear.
• Before entering tracking mode (ACQ
= 1), software must wait a given time, t
ACQ
(See 4.8
Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL
control register (PCTL).
• Software must wait a given time, t
AL
, after entering tracking mode before selecting the PLL as the
clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
4.3.6 Programming the PLL
Use the following procedure to program the PLL. For reference, the variables used and their meaning are
shown in Table 4-1.
NOTE
The round function in the following equations means that the real number
should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f
BUSDES
.
2. Calculate the desired VCO frequency (four times the desired bus frequency).
f
VCLKDES
= 4 x f
BUSDES
3. Choose a practical PLL (crystal) reference frequency, f
RCLK
. Typically, the reference crystal is 1–8
MHz.
Frequency errors to the PLL are corrected at a rate of f
RCLK
.
For stability and lock time reduction, this rate must be as fast as possible. The VCO frequency must
be an integer multiple of this rate. The relationship between the VCO frequency, f
VCLK
, and the
reference frequency, f
RCLK
, is:
f
VCLK
= (N) (f
RCLK
)
N, the range multiplier, must be an integer.
Table 4-1. Variable Definitions
Variable Definition
f
BUSDES
Desired bus clock frequency
f
VCLKDES
Desired VCO clock frequency
f
RCLK
Chosen reference crystal frequency
f
VCLK
Calculated VCO clock frequency
f
BUS
Calculated bus clock frequency
f
NOM
Nominal VCO center frequency
f
VRS
Programmed VCO center frequency