Datasheet

Clock Generator Module (CGM)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
82 Freescale Semiconductor
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
4.3.8 Base Clock Selector Circuit.).
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L controls the hardware center-of-range frequency, f
VRS
. VPR1:VPR0 cannot be written when the
PLLON bit is set. Reset clears these bits. (See 4.3.3 PLL Circuits, 4.3.6 Programming the PLL, and
4.5.5 PLL VCO Range Select Register.)
NOTE
Verify that the value of the VPR1 and VPR0 bits in the PCTL register are
appropriate for the given reference and VCO clock frequencies before
enabling the PLL. See 4.3.6 Programming the PLL for detailed instructions
on selecting the proper value for these control bits.
4.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual
operation (AUTO = 0), clear the ACQ
bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
Table 4-4. VPR1 and VPR0 Programming
VPR1 and VPR0 E
VCO Power-of-Two
Range Multiplier
00 0 1
01 1 2
10
2
(1)
1. Do not program E to a value of 3.
4
Address: $0037
Bit 7654321Bit 0
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:00000000
= Unimplemented R = Reserved
Figure 4-5. PLL Bandwidth Control Register (PBWC)