Datasheet

MSCAN08 Controller (MSCAN08)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
152 Freescale Semiconductor
12.13.11 MSCAN08 Transmit Error Counter
This read-only register reflects the status of the MSCAN08 transmit error counter.
NOTE
Both error counters may only be read when in sleep or soft reset mode.
12.13.12 MSCAN08 Identifier Acceptance Registers
On reception each message is written into the background receive buffer. The CPU is only signalled to
read the message, however, if it passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message will be overwritten by the next message (dropped).
The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3 registers of incoming
messages in a bit by bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only
the first two (CIDMR0/CIDMR1 and CIDAR0/CIDAR1) are applied.
Address: $050F
Bit 7654321Bit 0
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Reset:00000000
= Unimplemented
Figure 12-26. Transmit Error Counter (CTXERR)
CIDAR0 Address: $0510
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by reset
CIDAR1 Address: $050511
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by reset
CIDAR2 Address: $0512
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by reset
CIDAR3 Address: $0513
Bit 7654321Bit 0
Read:
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Write:
Reset: Unaffected by reset
Figure 12-27. Identifier Acceptance Registers
(CIDAR0–CIDAR3)