Datasheet

Input/Output (I/O) Ports
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
166 Freescale Semiconductor
Figure 13-15. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-5 summarizes the operation of the port D pins.
13.6.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the eight port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
Table 13-5. Port D Pin Functions
PTDPUE
Bit
DDRD
Bit
PTD
Bit
I/O Pin
Mode
Accesses to DDRD Accesses to PTD
Read/Write Read Write
10
X
(1)
1. X = Don’t care
Input, V
DD
(2)
2. I/O pin pulled up to V
DD
by internal pullup device.
DDRD7–DDRD0 Pin
PTD7–PTD0
(3)
3. Writing affects data register, but does not affect input.
00X
Input, Hi-Z
(4)
4. Hi-Z = High impedance
DDRD7–DDRD0 Pin
PTD7–PTD0
(3)
X 1 X Output DDRD7–DDRD0 PTD7–PTD0 PTD7–PTD0
Address: $000F
Bit 7654321Bit 0
Read:
PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Write:
Reset:00000000
Figure 13-16. Port D Input Pullup Enable Register (PTDPUE)
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
READ PTD ($0003)
PTDx
DDRDx
PTDx
INTERNAL DATA BUS
VDD
INTERNAL
PTDPUEx
PULLUP
DEVICE